{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,7]],"date-time":"2025-11-07T04:04:09Z","timestamp":1762488249183,"version":"build-2065373602"},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T00:00:00Z","timestamp":1749600000000},"content-version":"vor","delay-in-days":71,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/501100009534","name":"Universit\u00e4t Stuttgart","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100009534","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2025,4]]},"abstract":"<jats:title>Abstract<\/jats:title>\n                  <jats:p>\n                    It has been known and explored for many years that low voltage testing amplifies the effect of a defect, increasing the size of a Small Delay Fault (SDF) and, in the best case, turning SDFs into easily detectable stuck-at-faults. It is often overlooked that\n                    <jats:inline-formula>\n                      <jats:alternatives>\n                        <jats:tex-math>$$V_{\\textrm{min}}$$<\/jats:tex-math>\n                        <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\">\n                          <mml:msub>\n                            <mml:mi>V<\/mml:mi>\n                            <mml:mtext>min<\/mml:mtext>\n                          <\/mml:msub>\n                        <\/mml:math>\n                      <\/jats:alternatives>\n                    <\/jats:inline-formula>\n                    testing poses an additional challenge to the test pattern generation method under process variations. The standard deviation of gate delays under\n                    <jats:inline-formula>\n                      <jats:alternatives>\n                        <jats:tex-math>$$V_{\\textrm{min}}$$<\/jats:tex-math>\n                        <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\">\n                          <mml:msub>\n                            <mml:mi>V<\/mml:mi>\n                            <mml:mtext>min<\/mml:mtext>\n                          <\/mml:msub>\n                        <\/mml:math>\n                      <\/jats:alternatives>\n                    <\/jats:inline-formula>\n                    is a multiple of that under nominal voltage. The increased variation will invalidate the efficiency of test patterns generated under nominal voltage and significantly reduce fault coverage. This paper presents the first algorithm for test pattern generation specifically tuned for\n                    <jats:inline-formula>\n                      <jats:alternatives>\n                        <jats:tex-math>$$V_{\\textrm{min}}$$<\/jats:tex-math>\n                        <mml:math xmlns:mml=\"http:\/\/www.w3.org\/1998\/Math\/MathML\">\n                          <mml:msub>\n                            <mml:mi>V<\/mml:mi>\n                            <mml:mtext>min<\/mml:mtext>\n                          <\/mml:msub>\n                        <\/mml:math>\n                      <\/jats:alternatives>\n                    <\/jats:inline-formula>\n                    testing which obtains higher fault coverage by smaller test sets than those generated for nominal voltage. The patterns applicable to other voltage levels can be derived from the pattern set generated under extreme variations at low supply voltage. Experimental results demonstrate that the proposed method produces test patterns that outperform N-detection test sets in terms of test set volume and fault efficiency across different voltage levels.\n                  <\/jats:p>","DOI":"10.1007\/s10836-025-06172-8","type":"journal-article","created":{"date-parts":[[2025,6,11]],"date-time":"2025-06-11T03:20:53Z","timestamp":1749612053000},"page":"209-219","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Small Delay Fault Testing with Multiple Voltages under Variations: Defect vs. Fault Coverage"],"prefix":"10.1007","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0009-0007-4214-1126","authenticated-orcid":false,"given":"Hanieh","family":"Jafarzadeh","sequence":"first","affiliation":[]},{"given":"Florian","family":"Klemme","sequence":"additional","affiliation":[]},{"given":"Hussam","family":"Amrouch","sequence":"additional","affiliation":[]},{"given":"Sybille","family":"Hellebrand","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4536-8290","authenticated-orcid":false,"given":"Hans-Joachim","family":"Wunderlich","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,6,11]]},"reference":[{"key":"6172_CR1","doi-asserted-by":"crossref","unstructured":"Hao H, McCluskey EJ (1993) Very-low-voltage testing for weak CMOS logic ICs. In Proc. IEEE international test conference (ITC), pp 275\u2013284","DOI":"10.1109\/TEST.1993.470686"},{"key":"6172_CR2","unstructured":"Tseng CW, Chen R, Nigh P, McCluskey EJ (2001) MinVDD testing for weak CMOS ICs. In Proc. IEEE VLSI test symposium (VTS), pp 339\u2013344"},{"key":"6172_CR3","doi-asserted-by":"crossref","unstructured":"Chang JT, McCluskey EJ (1996) Detecting delay flaws by very-low-voltage testing. In Proc. international test conference (ITC), pp 367\u2013376","DOI":"10.1109\/TEST.1996.556983"},{"key":"6172_CR4","doi-asserted-by":"crossref","unstructured":"Renovell M, Huc P, Bertrand Y (1996) Bridging fault coverage improvement by power supply control. In Proc. VLSI test symposium (VTS), pp 338\u2013343","DOI":"10.1109\/VTEST.1996.510877"},{"issue":"19","key":"6172_CR5","first-page":"1","volume":"42","author":"R Rodriguez-Montanes","year":"2006","unstructured":"Rodriguez-Montanes R, Arumi D, Figueras J (2006) Effectiveness of very low voltage testing of bridging defects. Electron Lett 42(19):1","journal-title":"Electron Lett"},{"issue":"5","key":"6172_CR6","doi-asserted-by":"publisher","first-page":"398","DOI":"10.1016\/j.mejo.2015.02.006","volume":"46","author":"H Villacorta","year":"2015","unstructured":"Villacorta H, Garcia-Gervacio J, Segura J, Champac V (2015) Low VDD and body bias conditions for testing bridge defects in the presence of process variations. Microelectron J 46(5):398\u2013403","journal-title":"Microelectron J"},{"key":"6172_CR7","unstructured":"Liao Y, Walker D (1996) Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages. In Proc. international test conference. Test and design validity, p. 767\u2013775"},{"key":"6172_CR8","doi-asserted-by":"crossref","unstructured":"Qian X, Han C, Singh AD (2012) Detection of gate-oxide defects with timing tests at reduced power supply. In Proc. IEEE VLSI test symposium (VTS), pp 120\u2013126","DOI":"10.1109\/VTS.2012.6231090"},{"key":"6172_CR9","doi-asserted-by":"crossref","unstructured":"Qian X, Singh AD (2010) Distinguishing resistive small delay defects from random parameter variations. In Proc. IEEE Asian test symposium (ATS), pp 325\u2013330","DOI":"10.1109\/ATS.2010.62"},{"key":"6172_CR10","doi-asserted-by":"crossref","unstructured":"Najafi-Haghi ZP, Wunderlich HJ (2021) Resistive open defect classification of embedded cells under variations. In Proc. IEEE latin american test symposium (LATS), pp 1\u20136","DOI":"10.1109\/LATS53581.2021.9651857"},{"key":"6172_CR11","doi-asserted-by":"crossref","unstructured":"Champac V, Gervacio JG (2018) Timing performance of nanometer digital circuits under process variations, Springer","DOI":"10.1007\/978-3-319-75465-9"},{"key":"6172_CR12","doi-asserted-by":"crossref","unstructured":"Eisele M, Berthold J, Schmitt-Landsiedel D, Mahnkopf R (1997) The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 5(4):360\u2013368","DOI":"10.1109\/92.645062"},{"key":"6172_CR13","doi-asserted-by":"crossref","unstructured":"Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich HJ (2024) Vmin testing under variations: Defect vs. fault coverage. In Proc. IEEE latin american test symposium (LATS), pp 1\u20136","DOI":"10.1109\/LATS65346.2025.10963937"},{"key":"6172_CR14","doi-asserted-by":"crossref","unstructured":"Pant P, Zelman J (2009) Understanding power supply droop during at-speed scan testing. In Proc. IEEE VLSI test symposium, pp 227\u2013232","DOI":"10.1109\/VTS.2009.46"},{"key":"6172_CR15","doi-asserted-by":"crossref","unstructured":"Li B, Fang L, Hsiao MS (2007) Efficient power droop aware delay fault testing. In Proc. IEEE international test conference (ITC), pp 1\u201310","DOI":"10.1109\/TEST.2007.4437597"},{"issue":"5","key":"6172_CR16","doi-asserted-by":"publisher","first-page":"715","DOI":"10.1007\/s10836-021-05979-5","volume":"37","author":"S Sadeghi-Kohan","year":"2021","unstructured":"Sadeghi-Kohan S, Hellebrand S, Wunderlich HJ (2021) Stress-aware periodic test of interconnects. J Electron Test 37(5):715\u2013728","journal-title":"J Electron Test"},{"key":"6172_CR17","unstructured":"Ali NZ, Zwolinski M, Al-Hashimi BM, Harrod P (2006) Dynamic voltage scaling aware delay fault testing. In Proc. IEEE european test symposium (ETS), pp 15\u201320"},{"key":"6172_CR18","doi-asserted-by":"crossref","unstructured":"Qian X, Han C, Singh AD (2012) Detection of gate-oxide defects with timing tests at reduced power supply. In Proc. IEEE VLSI test symposium (VTS), pp 120\u2013126","DOI":"10.1109\/VTS.2012.6231090"},{"key":"6172_CR19","doi-asserted-by":"crossref","unstructured":"Karel A, Azais F, Comte M, Galliere JM, Renovell M, Singh K (2017) Detection of resistive open and short defects in FDSOI under delay-based test: Optimal VDD and body biasing conditions. In Proc. IEEE European test symposium (ETS), pp 1\u20132","DOI":"10.1109\/ETS.2017.7968208"},{"key":"6172_CR20","doi-asserted-by":"crossref","unstructured":"Zhang X, Bai X (2008) Process variability-induced timing failures, a challenge in nanometer CMOS low-power design. In Proc. IEEE international conference on integrated circuit design and technology and tutorial, pp 159\u2013162","DOI":"10.1109\/ICICDT.2008.4567269"},{"key":"6172_CR21","doi-asserted-by":"crossref","unstructured":"Sadeghi-Kohan S, Hellebrand S (2020) Dynamic multi-frequency test method for hidden interconnect defects. In Proc. IEEE VLSI test symposium (VTS), pp 1\u20136","DOI":"10.1109\/VTS48691.2020.9107591"},{"key":"6172_CR22","doi-asserted-by":"crossref","unstructured":"Galarza-Medina FJ, Garc\u00eda-Gervacio JL, Champac V, Orailoglu A (2012) Small-delay defects detection under process variation using inter-path correlation. In Proc. IEEE VLSI test symposium (VTS), pp 127\u2013132","DOI":"10.1109\/VTS.2012.6231091"},{"key":"6172_CR23","doi-asserted-by":"crossref","unstructured":"Peng K, Yilmaz M, Chakrabarty K, Tehranipoor M (2013) Crosstalk- and process variations-aware high-quality tests for small-delay defects. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(6):1129\u20131142 2013","DOI":"10.1109\/TVLSI.2012.2205026"},{"key":"6172_CR24","doi-asserted-by":"crossref","unstructured":"Sauer M, Polian I, Imhof ME, Mumtaz A, Schneider E, Czutro A, Wunderlich HJ, Becker B (2014) Variation-aware deterministic ATPG. In Proc. IEEE European test symposium (ETS), pp 1\u20136","DOI":"10.1109\/ETS.2014.6847806"},{"key":"6172_CR25","doi-asserted-by":"crossref","unstructured":"Jafarzadeh H, Klemme F, Reimer JD, Najafi-Haghi ZP, Amrouch H, Hellebrand S, Wunderlich HJ (2023) Robust pattern generation for small delay faults under process variations. In Proc. IEEE international test conference (ITC), pp 111\u2013116","DOI":"10.1109\/ITC51656.2023.00026"},{"key":"6172_CR26","doi-asserted-by":"crossref","unstructured":"Natarajan S, Agostinelli M, Akbar S, Bost M, Bowonder A, Chikarmane V, Chouksey S, Dasgupta A, Fischer K,\u00a0Fu Q et\u00a0al (2014) A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 $$\\mu $$m SRAM cell size. In Proc. IEEE international electron devices meeting, pp 3\u20137","DOI":"10.1109\/IEDM.2014.7046976"},{"key":"6172_CR27","unstructured":"Khandelwal S, Duarte JP, Medury AS, Venugopalan S, Paydavosi N, Lu DD, Lin CH, Dunga M, Yao S, Morshed T et\u00a0al (2015) BSIM-CMG 110.0. 0: Multi-gate MOSFET compact model: technical manual. BSIM Group UC Berkeley"},{"issue":"9","key":"6172_CR28","doi-asserted-by":"publisher","first-page":"3127","DOI":"10.1109\/TCSI.2020.2990672","volume":"67","author":"H Amrouch","year":"2020","unstructured":"Amrouch H, Pahwa G, Gaidhane AD, Dabhi CK, Klemme F, Prakash O, Chauhan YS (2020) Impact of variability on processor performance in negative capacitance FinFET technology. IEEE Trans Circuits Syst I Regul Pap 67(9):3127\u20133137","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"12","key":"6172_CR29","doi-asserted-by":"publisher","first-page":"5233","DOI":"10.1109\/TCSI.2022.3201431","volume":"69","author":"F Klemme","year":"2022","unstructured":"Klemme F, Amrouch H (2022) Efficient learning strategies for machine learning-based characterization of aging-aware cell libraries. IEEE Trans Circuits Syst I Regul Pap 69(12):5233\u20135246","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"6","key":"6172_CR30","doi-asserted-by":"publisher","first-page":"2569","DOI":"10.1109\/TCSI.2021.3069664","volume":"68","author":"F Klemme","year":"2021","unstructured":"Klemme F, Amrouch H (2021) Machine learning for on-the-fly reliability-aware cell library characterization. IEEE Trans Circuits Syst I Regul Pap 68(6):2569\u20132579","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"6172_CR31","doi-asserted-by":"crossref","unstructured":"Martins M, Matos JM, Ribas RP, Reis A, Schlinker G, Rech L, Michelsen J (2015) Open cell library in 15nm FreePDK technology. In Proc. international symposium on physical design, pp. 171\u2013178","DOI":"10.1145\/2717764.2717783"},{"issue":"5","key":"6172_CR32","doi-asserted-by":"publisher","first-page":"829","DOI":"10.1109\/TCAD.2016.2598560","volume":"36","author":"E Schneider","year":"2016","unstructured":"Schneider E, Kochte MA, Holst S, Wen X, Wunderlich HJ (2016) GPU-accelerated simulation of small delay faults. IEEE Trans Comput Aided Des Integr Circuits Syst 36(5):829\u2013841","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"6172_CR33","doi-asserted-by":"publisher","first-page":"126","DOI":"10.1109\/43.3140","volume":"7","author":"MH Schulz","year":"1988","unstructured":"Schulz MH, Trischler E, Sarfert TM (1988) Socrates: A highly efficient automatic test pattern generation system. IEEE Trans Comput Aided Des Integr Circuits Syst 7(1):126\u2013137","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6172_CR34","doi-asserted-by":"crossref","unstructured":"Eggersgl\u00fc\u00df S, Drechsler R (2011) As-robust-as-possible test generation in the presence of small delay defects using pseudo-boolean optimization. In Proc. design, automation & test in Europe, pp 1\u20136","DOI":"10.1109\/DATE.2011.5763207"},{"key":"6172_CR35","unstructured":"Chen LC, Gupta SK, Breuer MA (1997) High quality robust tests for path delay faults. In Proc. IEEE VLSI test symposium (VTS), pp 88\u201393"},{"issue":"3","key":"6172_CR36","doi-asserted-by":"publisher","first-page":"372","DOI":"10.1109\/43.833205","volume":"19","author":"I Pomeranz","year":"2000","unstructured":"Pomeranz I, Reddy SM (2000) On n-detection test sets and variable n-detection test sets for transition faults. IEEE Trans Comput Aided Des Integr Circuits Syst 19(3):372\u2013383","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6172_CR37","doi-asserted-by":"crossref","unstructured":"Jafarzadeh H, Klemme F, Amrouch H, Hellebrand S, Wunderlich HJ (2024) Time and space optimized storage-based BIST under multiple voltages and variations. In Proc. IEEE European test symposium (ETS), pp 1\u20136","DOI":"10.1109\/ETS61313.2024.10567295"},{"key":"6172_CR38","doi-asserted-by":"crossref","unstructured":"Jafarzadeh H, Klemme F, Reimer JD, Amrouch H, Hellebrand S, Wunderlich HJ (2024) Minimizing pvt-variability by exploiting the zero temperature coefficient (ztc) for robust delay fault testing. In Proc. IEEE international test conference (ITC), pp 26\u201330","DOI":"10.1109\/ITC51657.2024.00013"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-025-06172-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-025-06172-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-025-06172-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,7]],"date-time":"2025-11-07T03:59:56Z","timestamp":1762487996000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-025-06172-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":38,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2025,4]]}},"alternative-id":["6172"],"URL":"https:\/\/doi.org\/10.1007\/s10836-025-06172-8","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2025,4]]},"assertion":[{"value":"31 October 2024","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"5 April 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 June 2025","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that they have no conflict of interest or competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflicts of Interest"}}]}}