{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,15]],"date-time":"2025-10-15T00:21:02Z","timestamp":1760487662941,"version":"build-2065373602"},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,8,1]],"date-time":"2025-08-01T00:00:00Z","timestamp":1754006400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Electron Test"],"published-print":{"date-parts":[[2025,8]]},"DOI":"10.1007\/s10836-025-06193-3","type":"journal-article","created":{"date-parts":[[2025,9,24]],"date-time":"2025-09-24T06:53:16Z","timestamp":1758696796000},"page":"503-523","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Modelling, Simulation, and FPGA Implementation of an Augmented Memory Built-in Self-Test Based Design for Bit-Oriented Memory"],"prefix":"10.1007","volume":"41","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6762-9263","authenticated-orcid":false,"given":"Aditya Kumar Singh","family":"Pundir","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6404-2782","authenticated-orcid":false,"given":"Pallavi","family":"Singh","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9822-8246","authenticated-orcid":false,"given":"Ramesh","family":"Kumar","sequence":"additional","affiliation":[]},{"given":"Manish Kumar","family":"Singla","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2025,9,24]]},"reference":[{"key":"6193_CR1","doi-asserted-by":"publisher","unstructured":"Dekker R, Beenker F, Thijssen L (1990) A realistic fault model and test algorithms for static random access memories. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 9(6).\u00a0https:\/\/doi.org\/10.1109\/43.55188","DOI":"10.1109\/43.55188"},{"key":"6193_CR2","doi-asserted-by":"crossref","unstructured":"Ramakrishna P, Vamshika T, Swathi M (2020) FPGA implementation of memory Bists using single interface. Int J Recent Technol Eng (IJRTE) ISSN: 2277\u20133878 (Online) 9(3)\u00a0","DOI":"10.35940\/ijrte.B3975.099320"},{"key":"6193_CR3","doi-asserted-by":"publisher","unstructured":"Goor VD, Zorian Y (1993) Effective march algorithms for testing single-order addressed memories. European Conference on Design Automation with the European Event in ASIC Design, Paris, France 499\u2013505. https:\/\/doi.org\/10.1109\/EDAC.1993.386425","DOI":"10.1109\/EDAC.1993.386425"},{"key":"6193_CR4","doi-asserted-by":"publisher","unstructured":"Wu CF, Huang CT, Cheng KL, Wu CW (2000) Simulation-based test algorithm generation for random access memories. Proceedings of 18th IEEE VLSI Test Symposium, Montreal, Quebec, Canada, 291\u2013296. https:\/\/doi.org\/10.1109\/VTEST.2000.843857","DOI":"10.1109\/VTEST.2000.843857"},{"key":"6193_CR5","doi-asserted-by":"publisher","unstructured":"Huang CT (2000) Jing-Reng Huang and Cheng- Wen Wu., A programmable built-in self-test core for embedded memories. Proceedings of 2000 Design Automation Conference. (IEEE Cat. No.00CH37106), Yokohama 11\u201312. https:\/\/doi.org\/10.1109\/ASPDAC.2000.835054","DOI":"10.1109\/ASPDAC.2000.835054"},{"key":"6193_CR6","doi-asserted-by":"publisher","unstructured":"Wang CW, Wu CF, Li J-F et al (2000) A built-in self-test and self-diagnosis scheme for embedded SRAM, Proceedings of the Ninth Asian Test Symposium, Taipei, Taiwan 45\u201350. https:\/\/doi.org\/10.1109\/ATS.2001.990267","DOI":"10.1109\/ATS.2001.990267"},{"key":"6193_CR7","doi-asserted-by":"publisher","unstructured":"Cheng C, Huang CT, Huang JR, Wu CW, Wey CJ, Tsai MC (2000) BRAINS: A BIST compiler for embedded memories. InProceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (pp. 299-307). IEEE.. https:\/\/doi.org\/10.1109\/MTDT.2005.25","DOI":"10.1109\/MTDT.2005.25"},{"issue":"4","key":"6193_CR8","doi-asserted-by":"publisher","first-page":"392","DOI":"10.1109\/92.863618","volume":"8","author":"JD Huang","year":"2000","unstructured":"Huang JD, Jou JY, Wen-Zen Shen (2000) ALTO: an iterative area\/performance trade-off algorithm for LUT-based FPGA technology mapping. IEEE Trans Very Large Scale Integr VLSI Syst 8(4):392\u2013400. https:\/\/doi.org\/10.1109\/92.863618","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"6193_CR9","doi-asserted-by":"publisher","unstructured":"Wu C-F, Huang C-T, Wang K-LCC-W, Wu C-W (2001) Simulation- based test algorithm generation and port scheduling for multi-port memories. Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232), Las Vegas, NV, USA 301\u2013306. https:\/\/doi.org\/10.1109\/DAC.2001.156155","DOI":"10.1109\/DAC.2001.156155"},{"key":"6193_CR10","doi-asserted-by":"publisher","unstructured":"Pundir KS, Sharma OP (2017) Fault tolerant reconfigurable hardware design using BIST on SRAM: A review, 2017 International Conference on Intelligent Computing and Control (I2C2), Coimbatore, 1\u201316. https:\/\/doi.org\/10.1109\/I2C2.2017.8321907","DOI":"10.1109\/I2C2.2017.8321907"},{"issue":"3","key":"6193_CR11","doi-asserted-by":"publisher","first-page":"844","DOI":"10.1109\/TVLSI.2016.2606499","volume":"25","author":"J Kim","year":"2017","unstructured":"Kim J, Lee W, Cho K, Kang S (2017) Hardware-efficient built-in redundancy analysis for memory with various spares. IEEE Trans Very Large Scale Integr VLSI Syst 25(3):844\u2013856. https:\/\/doi.org\/10.1109\/TVLSI.2016.2606499","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"12","key":"6193_CR12","first-page":"3023","volume":"12","author":"AKS Pundir","year":"2017","unstructured":"Pundir AKS, Sharma OP (2017) A modified novel memory-testing approach for bit-oriented SRAM. Int J Appl Eng Res 12(12):3023\u20133028","journal-title":"Int J Appl Eng Res"},{"key":"6193_CR13","doi-asserted-by":"publisher","unstructured":"Haron NZ, Yunus SAMJ, Aziz ASA (2007) Modeling and simulation of microcode memory built-in self test architecture for embedded memories. 2007 Int Symp Commun Inf Technol Proc ISC 2007: 136\u2013139. https:\/\/doi.org\/10.1109\/ISCIT.2007.4392000","DOI":"10.1109\/ISCIT.2007.4392000"},{"issue":"3","key":"6193_CR14","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1367045.1367063","volume":"13","author":"T Pecenka","year":"2008","unstructured":"Pecenka T, Sekanina L, Kotasek Z (2008) Evolution of synthetic RTL benchmark circuits with predefined testability. ACM Transactions on Design Automation of Electronic Systems (TODAES) 13(3):1\u201321. https:\/\/doi.org\/10.1145\/1367045.1367063","journal-title":"ACM Transactions on Design Automation of Electronic Systems (TODAES)"},{"key":"6193_CR15","doi-asserted-by":"publisher","unstructured":"Peter S, Bottorff ME, Schwass, Villante FJ (1970) An automatic system approach to the problem of memory circuit testing & fault diagnosis. In Proceedings of the 7th Design Automation Workshop (DAC \u201870). Association for Computing Machinery, New York, NY, USA, (December) 95\u201399. https:\/\/doi.org\/10.1145\/800160.805116","DOI":"10.1145\/800160.805116"},{"issue":"6","key":"6193_CR16","doi-asserted-by":"publisher","first-page":"1101","DOI":"10.1109\/TCAD.2006.885828","volume":"26","author":"JC Yeh","year":"2007","unstructured":"Yeh JC, Cheng KL, Chou YF, Wu CW (2007) Flash memory testing and built-in self-diagnosis with march-like test algorithms. IEEE Trans Comput Des Integr Circuits Syst. 26(6):1101\u20131112. https:\/\/doi.org\/10.1109\/TCAD.2006.885828","journal-title":"IEEE Trans Comput Des Integr Circuits Syst."},{"key":"6193_CR17","doi-asserted-by":"publisher","unstructured":"Gunavathi K, Paramasivam K, SubashiniLavanya P, Umamageswaran M (2006) A novel BIST TPG for testing of VLSI circuits. First Int Conf Industrial Inform Syst 109\u2013114. https:\/\/doi.org\/10.1109\/ICIIS.2006.365646","DOI":"10.1109\/ICIIS.2006.365646"},{"key":"6193_CR18","doi-asserted-by":"publisher","unstructured":"\u00d6hler P, Bosio A, Di Natale G, Hellebrand S (2008) A modular memory BIST for optimized memory re- pair. Proc. \u2013\u200914th IEEE Int. On-Line Test. Symp 171\u2013172. https:\/\/doi.org\/10.1109\/IOLTS.2008.30","DOI":"10.1109\/IOLTS.2008.30"},{"key":"6193_CR19","doi-asserted-by":"publisher","unstructured":"Zordan LB, Bosio A, Dilillo L, Girard P, Pravossoudovitch S, Virazel A, Badereddine N (2011) Optimized March test flow for detecting memory faults in SRAM devices under bit line coupling. 14th IEEE Int Symp Des Diagnostics Electron Circuits Syst 353\u2013358. https:\/\/doi.org\/10.1109\/DDECS.2011.5783110.","DOI":"10.1109\/DDECS.2011.5783110"},{"key":"6193_CR20","doi-asserted-by":"publisher","first-page":"1165","DOI":"10.1109\/MTDT.2005.25","volume":"1","author":"D Xiaogang","year":"2005","unstructured":"Xiaogang D, Mukherjee N, Cheng WT, August SM (2005) Full-speed field-programmable memory BIST architecture. Proceedings of Int Test Conf 1:1165\u20131173. https:\/\/doi.org\/10.1109\/MTDT.2005.25","journal-title":"Proceedings of Int Test Conf"},{"issue":"September","key":"6193_CR21","doi-asserted-by":"publisher","first-page":"276","DOI":"10.1109\/DSD.2005.56","volume":"1","author":"M Fischerov\u00e1","year":"2005","unstructured":"Fischerov\u00e1 M, \u0160imla\u0161t\u00edk M (2005) MemBIST applet for learning principles of memory testing and generating memory BIST. Proc DSD\u2019 2005 8th Euromicro Conf Digit Syst Des (DSD\u201905) 1(September):276\u2013281. https:\/\/doi.org\/10.1109\/DSD.2005.56","journal-title":"Proc DSD\u2019 2005 8th Euromicro Conf Digit Syst Des (DSD\u201905)"},{"issue":"4","key":"6193_CR22","doi-asserted-by":"publisher","first-page":"560","DOI":"10.1145\/944027.944037","volume":"8","author":"Dirk Niggemeyer","year":"2003","unstructured":"Niggemeyer Dirk, Rudnick Elizabeth M (2003) A data acquisition methodology for on-chip repair of embedded memories. ACM Trans Des Autom Electron Syst 8(4):560\u2013576. https:\/\/doi.org\/10.1145\/944027.944037","journal-title":"ACM Trans Des Autom Electron Syst"},{"issue":"September","key":"6193_CR23","doi-asserted-by":"publisher","first-page":"31","DOI":"10.1145\/3339851","volume":"24","author":"KH Choi","year":"2019","unstructured":"Choi KH, Jun J, Kim M, Kim SW (2019) Reducing DRAM refresh rate using retention time aware universal hashing redundancy repair, ACM trans. Des. Autom Electron Syst 24, 5, Article 53 ((September):31. https:\/\/doi.org\/10.1145\/3339851","journal-title":"Autom Electron Syst"},{"key":"6193_CR24","doi-asserted-by":"publisher","unstructured":"Venkatesh R, Kumar S, Philip J, Shukla S (2002) A fault modeling technique to test memory BIST algorithms. Rec IEEE Int Work Mem Technol Des Test 109\u2013116.\u00a0https:\/\/doi.org\/10.1109\/MTDT.2002.1029771","DOI":"10.1109\/MTDT.2002.1029771"},{"key":"6193_CR25","doi-asserted-by":"publisher","unstructured":"Jee (2002) Defect-oriented analysis of memory BIST tests. Proceedings of the 2002 IEEE International Workshop on Memory Technology, Design and Testing (MTDT2002) 7\u201311. https:\/\/doi.org\/10.1109\/MTDT.2002.1029756","DOI":"10.1109\/MTDT.2002.1029756"},{"key":"6193_CR26","doi-asserted-by":"publisher","unstructured":"Niamat M (2013) FPGA memory testing technique using BIST. Midwest Symp. Circuits System. 473\u2013476. https:\/\/doi.org\/10.1109\/MWSCAS.2013.6674688","DOI":"10.1109\/MWSCAS.2013.6674688"},{"key":"6193_CR27","doi-asserted-by":"publisher","unstructured":"Zordan LB, Bosio A, Dilillo L, Girard P, Todri A, Virazel A, Badereddine N (2013) A built-in scheme for testing and repairing voltage regulators of low-power SRAMs. Proceeding of IEEE VLSI Test Symp 1\u20136. https:\/\/doi.org\/10.1109\/VTS.2013.6548894","DOI":"10.1109\/VTS.2013.6548894"},{"key":"6193_CR28","doi-asserted-by":"publisher","unstructured":"Wu TY, Chen PY, Wu CW, Kwai DM (2010) Improving testing and diagnosis efficiency for regular memory arrays. Proc 2010 Int Symp VLSI Des Autom Test VLSI-DAT 100\u2013103. https:\/\/doi.org\/10.1109\/VDAT.2010.5496701","DOI":"10.1109\/VDAT.2010.5496701"},{"key":"6193_CR29","doi-asserted-by":"publisher","unstructured":"Niamat M, Lalla M, Kim J (2009) Testing faults in SRAM memory of virtex-4 FPGA. Midwest Symp Circuits Syst 965\u2013970. https:\/\/doi.org\/10.1109\/MWSCAS.2009.5235927","DOI":"10.1109\/MWSCAS.2009.5235927"},{"key":"6193_CR30","doi-asserted-by":"publisher","unstructured":"Bocquillon G, Foucard F, Miller N, Buard R, Leveugle C, Daniel S, Rakers T, Carriere V, Pouget, Velazco R (2007) Highlights of laser testing capabilities regarding the understanding of SEE in SRAM based FPGAs. Proceedings of Eur Conf Radiation its Effects Components Syst. RADECS, 1\u20136. https:\/\/doi.org\/10.1109\/RADECS.2007.5205500","DOI":"10.1109\/RADECS.2007.5205500"},{"key":"6193_CR31","doi-asserted-by":"publisher","unstructured":"Noor NQM, Yusof Y, Saparon A (2009) Low area FSM-based memory BIST for synchronous SRAM. Proc 2009 5th Int Colloq Signal Process its Appl CSPA 409\u2013412. https:\/\/doi.org\/10.1109\/CSPA.2009.5069261.","DOI":"10.1109\/CSPA.2009.5069261"},{"key":"6193_CR32","doi-asserted-by":"publisher","unstructured":"Zhang Z, Wen Z, Chen L (2009) BIST approach for testing embedded memory blocks in system-on-chips. 2009 IEEE Circuits Syst. Int. Conf. Test. Diagnosis, ICTD\u201909. 1\u20133. https:\/\/doi.org\/10.1109\/CAS-ICTD.2009.4960791","DOI":"10.1109\/CAS-ICTD.2009.4960791"},{"key":"6193_CR33","doi-asserted-by":"publisher","unstructured":"Zhang Z, Wen Z, Chen L, Zhou T, Zhang F (2008) BIST approach for testing configurable logic and memory resources in FPGAs. Proc IEEE Asia-Pacific Conf Circuits Syst APCCAS 2: 1767\u20131770. https:\/\/doi.org\/10.1109\/APCCAS.2008.4746383","DOI":"10.1109\/APCCAS.2008.4746383"},{"key":"6193_CR34","doi-asserted-by":"publisher","unstructured":"Haron NZ, Yunus SAMJ, Aziz ASA (2007) Modeling and simulation of microcode memory built-in self-test architecture for embedded memories, International Symposium on Communications and Information Technologies 136\u2013139. https:\/\/doi.org\/10.1109\/ISCIT.2007.4392000","DOI":"10.1109\/ISCIT.2007.4392000"},{"issue":"1","key":"6193_CR35","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/LATW.2015.7102493","volume":"I","author":"P Bernardi","year":"2015","unstructured":"Bernardi P, Ciganda L, Reorda MS, Hamdioui S (2015) SW-based transparent in-field memory testing. 2015 16th Latin-American Test Symp LATS 2015 I(1):1\u20136. https:\/\/doi.org\/10.1109\/LATW.2015.7102493. (March)","journal-title":"2015 16th Latin-American Test Symp LATS 2015"},{"key":"6193_CR36","doi-asserted-by":"publisher","DOI":"10.1049\/iet-cds.2018.5218","author":"AdityaKumar Singh Pundir","year":"2019","unstructured":"Singh Pundir Aditya Kumar (2019) Novel modified memory built in self\u2010repair (MMBISR) for SRAM using hybrid redundancy\u2010analysis technique. IET Circuits, Devices & Systems. https:\/\/doi.org\/10.1049\/iet-cds.2018.5218","journal-title":"IET Circuits, Devices & Systems"},{"key":"6193_CR37","doi-asserted-by":"publisher","unstructured":"Vannal NS, Siddamal SV, Bidaralli SV, Bhille MS (2015) Design and testing of combinational logic circuits using built in self test scheme for FPGAs. Proceedings of 2015 5th Int Conf Commun Syst Netw Technol CSNT I(I): 903\u2013907, 2015. https:\/\/doi.org\/10.1109\/CSNT.2015.151","DOI":"10.1109\/CSNT.2015.151"},{"key":"6193_CR38","doi-asserted-by":"publisher","unstructured":"Shirur YJM, Lakshmi HR, Chakravarthi VS (2014) Implementation of Area Efficient Hybrid MBIST for Memory Clusters in Asynchronous SoC.2014 Fifth International Symposium on Electronic System Design 226\u2013227. https:\/\/doi.org\/10.1109\/ISED.2014.57","DOI":"10.1109\/ISED.2014.57"}],"container-title":["Journal of Electronic Testing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-025-06193-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s10836-025-06193-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s10836-025-06193-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,10,14]],"date-time":"2025-10-14T04:36:30Z","timestamp":1760416590000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s10836-025-06193-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,8]]},"references-count":38,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2025,8]]}},"alternative-id":["6193"],"URL":"https:\/\/doi.org\/10.1007\/s10836-025-06193-3","relation":{},"ISSN":["0923-8174","1573-0727"],"issn-type":[{"type":"print","value":"0923-8174"},{"type":"electronic","value":"1573-0727"}],"subject":[],"published":{"date-parts":[[2025,8]]},"assertion":[{"value":"10 January 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 August 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"24 September 2025","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"Authors have no conflict of Interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}