{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T16:17:32Z","timestamp":1774369052908,"version":"3.50.1"},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2012,6,16]],"date-time":"2012-06-16T00:00:00Z","timestamp":1339804800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Intell Manuf"],"published-print":{"date-parts":[[2014,4]]},"DOI":"10.1007\/s10845-012-0671-4","type":"journal-article","created":{"date-parts":[[2012,6,18]],"date-time":"2012-06-18T12:16:48Z","timestamp":1340021808000},"page":"263-271","source":"Crossref","is-referenced-by-count":7,"title":["Analyzing and comparing the AES architectures for their power consumption"],"prefix":"10.1007","volume":"25","author":[{"given":"Ahmet","family":"Dogan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. Berna","family":"Ors","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Gokay","family":"Saldamli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2012,6,16]]},"reference":[{"key":"671_CR1","doi-asserted-by":"crossref","unstructured":"Bertoni, G., Macchetti, M., Negri, L., & Fragneto, P. (2004). Power-efficient ASIC synthesis of cryptographic sboxes. In Proceedings of the 14th Great Lakes symposium on VLSI (GLSVLSI) (pp. 277\u2013281), ACM.","DOI":"10.1145\/988952.989019"},{"key":"671_CR2","first-page":"1626","volume-title":"Proceedings of AFRICACRYPT, Lecture notes in computer science Vol. 5023","author":"P. Bulens","year":"2008","unstructured":"Bulens P., Standaert F. X., Quisquater J. J., Pellegrin P., Rouvroy G. (2008) Implementation of the AES-128 on virtex-5 FPGAs. In: Vaudenay S. (Ed.) Proceedings of AFRICACRYPT, Lecture notes in computer science Vol. 5023. Springer, Berlin, p 1626"},{"key":"671_CR3","first-page":"288","volume-title":"Proceedings of the international conference on smart card research and applications (CARDIS), Lecture notes in computer science Vol. 1820","author":"J. Daemen","year":"1998","unstructured":"Daemen J., Rijmen V. (1998) The block cipher Rijndael. In: Quisquater J. J., Schneier B. (Eds.) Proceedings of the international conference on smart card research and applications (CARDIS), Lecture notes in computer science Vol. 1820. Springer, Louvain-la-Neuve, Belgium, pp 288\u2013296"},{"issue":"6","key":"671_CR4","doi-asserted-by":"crossref","first-page":"522","DOI":"10.1109\/MDT.2007.178","volume":"24","author":"T. Eisenbarth","year":"2007","unstructured":"Eisenbarth T., Kumar S. (2007) A survey of lightweight-cryptography implementations. Design Test of Computers, IEEE 24(6): 522\u2013533","journal-title":"Design Test of Computers, IEEE"},{"issue":"1","key":"671_CR5","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1049\/ip-ifs:20055006","volume":"152","author":"M. Feldhofer","year":"2005","unstructured":"Feldhofer M., Wolkerstorfer J., Rijmen V. (2005) AES implementation on a grain of sand. IEE Proceedings Information Security 152(1): 13\u201320","journal-title":"IEE Proceedings Information Security"},{"key":"671_CR6","doi-asserted-by":"crossref","first-page":"235","DOI":"10.1007\/978-0-387-71817-0_10","volume-title":"Cryptographic engineering","author":"K. Gaj","year":"2009","unstructured":"Gaj K., Chodowiec P. (2009) Fpga and asic implementations of the aes. In: Koc C. (Ed.) Cryptographic engineering. Springer, Berlin, pp 235\u2013294"},{"key":"671_CR7","doi-asserted-by":"crossref","unstructured":"Good, T., & Benaissa, M. (2005) AES on FPGA from the fastest to the smallest. In J. Rao & B. Sunar (Eds.), Proceedings of the 7th international workshop on cryptographic hardware and embedded systems (CHES), Lecture notes in computer science (Vol. 3659, pp. 427\u2013440). Berlin: Springer.","DOI":"10.1007\/11545262_31"},{"issue":"11","key":"671_CR8","doi-asserted-by":"crossref","first-page":"1498","DOI":"10.1109\/TC.2008.80","volume":"57","author":"T. Guneysu","year":"2008","unstructured":"Guneysu T., Kasper T., Novotny M., Paar C., Rupp A. (2008) Cryptanalysis with copacobana. IEEE Transactions on Computers 57(11): 1498\u20131513","journal-title":"IEEE Transactions on Computers"},{"key":"671_CR9","unstructured":"Hodjat, A., Schaumont, P., & Verbauwhede, I. (2004). Architectural design features of a programmable high throughput aes coprocessor. In Proceedings of the international conference on information technology: Coding and computing (ITCC), IEEE."},{"key":"671_CR10","doi-asserted-by":"crossref","unstructured":"Hodjat, A., & Verbauwhede, I. (2003). Speed-area trade-off for 10 to 100 gbits\/s throughput AES processor. In Proceedings of the 37th Asilomar conference on signals, systems and computers (pp. 2147\u20132150).","DOI":"10.1109\/ACSSC.2003.1292360"},{"key":"671_CR11","unstructured":"Hodjat, A., & Verbauwhede, I. (2004a). A 21.54 gbits\/s fully pipelined AES processor on fpga. In Proceedings of the 12th annual symposium on field-programmable custom computing machines (FCCM), IEEE."},{"key":"671_CR12","doi-asserted-by":"crossref","unstructured":"Hodjat, A., & Verbauwhede, I. (2004b). Minimum area cost for a 30 to 70 gbits\/s AES processor. In Proceedings of the Annual Symposium on VLSI Emerging Trends in VLSI Systems Design (ISVLST) (pp. 83\u201388). IEEE Computer Society.","DOI":"10.1109\/ISVLSI.2004.1339512"},{"key":"671_CR13","unstructured":"Hodjat, A., Verbauwhede, I. (2004c). Minimum area cost for a 30 to 70 gbits\/s AES processor. In Proceedings of the annual symposium on VLSI emerging trends in VLSI systems design (ISVLSI), IEEE Computer Society."},{"issue":"4","key":"671_CR14","doi-asserted-by":"crossref","first-page":"366","DOI":"10.1109\/TC.2006.49","volume":"55","author":"A. Hodjat","year":"2006","unstructured":"Hodjat A., Verbauwhede I. (2006) Area-throughput trade-offs for fully pipelined 30 to 70 gbits\/s AES processors. IEEE Transactions On Computers 55(4): 366\u2013372","journal-title":"IEEE Transactions On Computers"},{"key":"671_CR15","unstructured":"Kaps, J. P. (2006). Cryptography for ultra-low power devices. Ph.D. thesis, Worcester Polytechnic Institue."},{"key":"671_CR16","unstructured":"Lenstra, A., & Verheul, E. (2000). Selecting cryptographic key sizes. In H. Imai & Y. Zheng (Eds.), Proceedings of the 3rd international workshop on practice and theory in public key cryptography (PKC 2000), Lecture notes in computer science (Vol. 1751, pp. 446\u2013465). Berlin: Springer."},{"issue":"5","key":"671_CR17","doi-asserted-by":"crossref","first-page":"635","DOI":"10.1007\/s10845-009-0256-z","volume":"21","author":"A. Levi","year":"2009","unstructured":"Levi A., Tasc\u0131 S. E., Lee Y. J., Bayramoglu E., Ergun M. (2009) Simple, extensible and flexible random key predistribution schemes for wireless sensor networks using reusable key pools. Journal of Intelligent Manufacturing 21(5): 635\u2013645","journal-title":"Journal of Intelligent Manufacturing"},{"issue":"1","key":"671_CR18","first-page":"39","volume":"2","author":"A. P. Ling","year":"2011","unstructured":"Ling A. P., Masao M. (2011) Selection of model in developing information security criteria for smart grid security system. Journal of Convergence 2(1): 39\u201346","journal-title":"Journal of Convergence"},{"key":"671_CR19","doi-asserted-by":"crossref","unstructured":"Nadeem, A., & Javed, M. (2005). A performance comparison of data encryption algorithms. In Information and communication technologies, 2005. ICICT 2005. First international conference on (pp. 84\u201389).","DOI":"10.1109\/ICICT.2005.1598556"},{"key":"671_CR20","unstructured":"National Institute of Standards and Technology. (2001). FIPS 197: Advanced Encryption Standard."},{"key":"671_CR21","unstructured":"National Institute of Standards and Technology. (1999). FIPS 46-3: Data Encryption Standard (reaffirmed 1999)."},{"key":"671_CR22","unstructured":"Paar, C. (1994). Efficient vlsi architectures for bit-parallel computations in galois fields. Ph.D. thesis, Institute for Experimental Mathematics, University of Essen."},{"key":"671_CR23","doi-asserted-by":"crossref","unstructured":"Radakovic, M., Obitko, M., & Macik, V. (2011). Dynamic explicitly specified behaviors in distributed agent-based industrial solutions. Journal of Intelligent Manufacturing. doi: 10.1007\/s10845-011-0593-6 .","DOI":"10.1007\/s10845-011-0593-6"},{"key":"671_CR24","unstructured":"Rudra, A., Dubey, P. K., Jutla, C. S., Kumar, V., Rao, J. R., & Rohatgi, P. (2001). Efficient Rijndael encryption implementation with composite field arithmetic. In \u00c7. K. Ko\u00e7, D. Naccache & C. Paar (Eds.), Proceedings of the 3rd international workshop on cryptograpic hardware and embedded systems (CHES), Lecture notes in computer science (Vol. 2162, pp. 171\u2013184). Paris, France: Springer."},{"issue":"1","key":"671_CR25","first-page":"23","volume":"2","author":"P. Sarkar","year":"2011","unstructured":"Sarkar P., Saha A. (2011) Security enhanced communication in wireless sensor networks using reed-muller codes and partially balanced incomplete block designs. Journal of Convergence 2(1): 23\u201330","journal-title":"Journal of Convergence"},{"key":"671_CR26","doi-asserted-by":"crossref","unstructured":"Satoh, A., Morioka, S. (2003). Hardware-focused performance comparison for the standard block ciphers aes, camellia, and triple-des. In Information security, Lecture notes in computer science (Vol. 2851, pp. 252\u2013266. Berlin: Springer.","DOI":"10.1007\/10958513_20"},{"issue":"1","key":"671_CR27","doi-asserted-by":"crossref","first-page":"66","DOI":"10.1504\/IJITCC.2010.035227","volume":"1","author":"S. J. Wang","year":"2010","unstructured":"Wang S. J., Tsai Y. R., Shen C. C., Chen P. Y. (2010) Hierarchical key derivation scheme for group-oriented communication systems. International Journal of Information Technology, Communications and Convergence 1(1): 66\u201376","journal-title":"International Journal of Information Technology, Communications and Convergence"},{"key":"671_CR28","unstructured":"Ward, R., & Molteno, T. (2003). Efficient hardware calculation of inverses in GF (28). Tech. rep., University of Otago, Physics Department."},{"issue":"1","key":"671_CR29","doi-asserted-by":"crossref","first-page":"4","DOI":"10.1504\/IJITCC.2010.035224","volume":"1","author":"B. Xie","year":"2010","unstructured":"Xie B., Kumar A., Zhao D., Reddy R., He B. (2010) On secure communication in integrated heterogeneous wireless networks. International Journal of Information Technology, Communications and Convergence 1(1): 4\u201343","journal-title":"International Journal of Information Technology, Communications and Convergence"}],"container-title":["Journal of Intelligent Manufacturing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10845-012-0671-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s10845-012-0671-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s10845-012-0671-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T17:20:28Z","timestamp":1743528028000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s10845-012-0671-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,6,16]]},"references-count":29,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2014,4]]}},"alternative-id":["671"],"URL":"https:\/\/doi.org\/10.1007\/s10845-012-0671-4","relation":{},"ISSN":["0956-5515","1572-8145"],"issn-type":[{"value":"0956-5515","type":"print"},{"value":"1572-8145","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,6,16]]}}}