{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,30]],"date-time":"2026-09-30T23:28:31Z","timestamp":1790810911654,"version":"4.1.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2022,2,17]],"date-time":"2022-02-17T00:00:00Z","timestamp":1645056000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2022,2,17]],"date-time":"2022-02-17T00:00:00Z","timestamp":1645056000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Mobile Netw Appl"],"published-print":{"date-parts":[[2022,6]]},"DOI":"10.1007\/s11036-021-01857-8","type":"journal-article","created":{"date-parts":[[2022,2,17]],"date-time":"2022-02-17T09:02:56Z","timestamp":1645088576000},"page":"1000-1018","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Trustworthy Scan Design and Testability Using Obfuscation and Logic Locking Scheme for Wireless Network Application"],"prefix":"10.1007","volume":"27","author":[{"given":"M. I.","family":"Shiny","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"M.","family":"Nirmala Devi","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2022,2,17]]},"reference":[{"key":"1857_CR1","doi-asserted-by":"publisher","first-page":"2205","DOI":"10.1109\/JIOT.2018.2883403","volume":"6","author":"H Xie","year":"2019","unstructured":"Xie H, Yan Z, Yao Z, Atiquzzaman M (2019) Data collection for security measurement in wireless SensorNetworks: a survey. IEEE Internet Things J 6:2205\u20132224","journal-title":"IEEE Internet Things J"},{"key":"1857_CR2","first-page":"711","volume":"58","author":"J Wang","year":"2019","unstructured":"Wang J, Gao Y, Liu W, Wu W, Lim SJ (2019) An asynchronous clustering and mobile data gathering Schema based on timer mechanism in wireless sensor networks. CMC Comput Mater Contin 58:711\u2013725","journal-title":"CMC Comput Mater Contin"},{"key":"1857_CR3","first-page":"9","volume":"21","author":"D Hely","year":"2004","unstructured":"Hely D, Flottes M-L, Bacel F, Rouzeyre B, Berard N, Renovell M (2004) Scan design and secure chip [secure IC testing]. 10th IEEE On-Line Testing and Robust SystemDesign (IOLTS ) Proceeding 21:9\u2013224","journal-title":"10th IEEE On-Line Testing and Robust SystemDesign (IOLTS ) Proceeding"},{"key":"1857_CR4","volume-title":"Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits","author":"ML Bushnell","year":"2000","unstructured":"Bushnell ML, Agrawal VD (2000) Essentials of electronic testing for digital, memory, and mixed-signal VLSI circuits. Kluwer, Norwell"},{"key":"1857_CR5","first-page":"234","volume-title":"21st IFIP\/IEEE International Conference on Very Large Scale Integration","author":"SS Ali","year":"2013","unstructured":"Ali SS, OzgurSinanoglu SM, Saeed RK (2013) New scan-based attack using only the test mode. In: 21st IFIP\/IEEE International Conference on Very Large Scale Integration, pp 234\u2013239"},{"key":"1857_CR6","first-page":"51","volume-title":"International Symposium on Defect and Fault Tolerance in VLSI System","author":"J Lee","year":"2005","unstructured":"Lee J, Tehranipoor M, Patel C, Plusquellic J (2005) Securing scan design using Lock & key Technique. In: International Symposium on Defect and Fault Tolerance in VLSI System, pp 51\u201362"},{"key":"1857_CR7","first-page":"455","volume-title":"Proceedings of 25th IEEE VLSI Test Symposium","author":"S Paul","year":"2004","unstructured":"Paul S, Chakraborty R, Bhunia S (2004) VIm-scan, a low overhead scan design approach for the protection of secret key in scan-based secure chips. In: Proceedings of 25th IEEE VLSI Test Symposium, pp 455\u2013460"},{"key":"1857_CR8","first-page":"7","volume-title":"11th IEEE Workshop on RTL and High-Level Testing","author":"K Fujiwara","year":"2010","unstructured":"Fujiwara K, Fujiwara H, Tamamoto H (2010) SREEP-2: SR- equivalent generator for secure and testable scan design. In: 11th IEEE Workshop on RTL and High-Level Testing, pp 7\u201312"},{"key":"1857_CR9","unstructured":"Das A, Karaklajic D, Verbauwhede I (2014) Secure mutual testing strategy for cryptographic SoCs. IACR Cryptol. ePrint Arch., 2014, 544"},{"issue":"5","key":"1857_CR10","doi-asserted-by":"publisher","first-page":"808_821","DOI":"10.1109\/TCAD.2015.2398423","volume":"34","author":"SS Ali","year":"2015","unstructured":"Ali SS, Saeed SM, Sinanoglu O, Karri R (2015) Novel test-mode- only scan attack and countermeasure for compression-based scan architectures. IEEE Trans Comput-Aided Design Integr Circuits Syst 34(5):808_821","journal-title":"IEEE Trans Comput-Aided Design Integr Circuits Syst"},{"issue":"11","key":"1857_CR11","doi-asserted-by":"publisher","first-page":"2080","DOI":"10.1109\/TCAD.2007.906483","volume":"2","author":"G Senegar","year":"2007","unstructured":"Senegar G, Mukhopadhyay D, Chowdhruy DR (2007) Secureflipped scan-chain model for crypto- architecture. IEEE transactions on Computer-Aided Design of Integrated Circuits andSystems 2(11):2080\u20132084","journal-title":"IEEE transactions on Computer-Aided Design of Integrated Circuits andSystems"},{"key":"1857_CR12","first-page":"19","volume-title":"Proceedings of 16thIEEE European Test Symposium (ETS)","author":"J Da Rolt","year":"2011","unstructured":"Da Rolt J, Di Natale G, Flottes M, Rouzeyre B (2011) Scan attack and countermeasures in the presence of scan response compactors. In: Proceedings of 16thIEEE European Test Symposium (ETS), pp 19\u201324"},{"key":"1857_CR13","doi-asserted-by":"publisher","first-page":"1243","DOI":"10.1109\/TR.2015.2464011","volume":"64","author":"RA Shafik","year":"2015","unstructured":"Shafik RA, Mathew J, Pradhan DK (2015) A low-cost unified design methodology for secure test and intellectual property Core protection. IEEE Transaction on Reliability 64:1243\u20131125","journal-title":"IEEE Transaction on Reliability"},{"key":"1857_CR14","first-page":"1","volume-title":"in Proc. 22nd IEEE Eur. Test Symp. (ETS)","author":"MD Silva","year":"2017","unstructured":"Silva MD, Flottes M-L, Natale GD, Rouzeyre B, Prinetto P, Restifo M (2017) Scan chain encryption for the test, diagnosis and debug of secure circuits. In: in Proc. 22nd IEEE Eur. Test Symp. (ETS), pp 1\u20136"},{"issue":"3","key":"1857_CR15","doi-asserted-by":"publisher","first-page":"1193","DOI":"10.1109\/TVLSI.2015.2437996","volume":"24","author":"J Zhang","year":"2016","unstructured":"Zhang J (2016) A practical logic obfuscation technique for hardware security. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24(3):1193\u20131197","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"1857_CR16","doi-asserted-by":"crossref","unstructured":"Rahman MT, Rahman MS, Wang H, Tajik S, Khalil W, Farahmandi F, Tehranipoor M (2020) Defense-in-depth: a recipe for logic locking to prevail. Integration 72:39\u201357","DOI":"10.1016\/j.vlsi.2019.12.007"},{"key":"1857_CR17","doi-asserted-by":"publisher","first-page":"17","DOI":"10.17485\/ijst\/2015\/v8i17\/62664","volume":"8","author":"R Bhakthavatchalu","year":"2015","unstructured":"Bhakthavatchalu R, Kannan SK, Nirmala Devi M (2015) Verilog design of programmable JTAG controller for digital VLSI ICs. Indian J Sci Technol 8:17","journal-title":"Indian J Sci Technol"},{"key":"1857_CR18","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/VTEST.2000.843824","volume-title":"Proc. of VLSI Test Symposium, Montreal","author":"R Sankaralingam","year":"2000","unstructured":"Sankaralingam R, Oruganti RR, Touba NA (2000) Static compaction techniques to control scan vector power dissipation. In: Proc. of VLSI Test Symposium, Montreal, pp 35\u201334"},{"key":"1857_CR19","doi-asserted-by":"publisher","first-page":"176","DOI":"10.1109\/TVLSI.2011.2120635","volume":"20","author":"Y Shi","year":"2012","unstructured":"Shi Y, NozomuTogawa MY, Ohtsuki T (2012) Robust secure scan design against scan-based differential cryptanalysis. IEEE Transactions on Very LargeScale Integration (VLSI) systems 20:176\u2013181","journal-title":"IEEE Transactions on Very LargeScale Integration (VLSI) systems"},{"issue":"2","key":"1857_CR20","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1007\/s10836-011-5204-0","volume":"27","author":"M Inoue","year":"2011","unstructured":"Inoue M, Yoneda T, Hasegawa M, Fujiwara H (2011) Balanced secure scan: partial ScanApproach for secret information protection. Journal of Electronic Testing: Theory and Applications (JETTA) 27(2):99\u2013108","journal-title":"Journal of Electronic Testing: Theory and Applications (JETTA)"},{"key":"1857_CR21","first-page":"321","volume-title":"Proceedings of VLSI test symposium","author":"U Chandran","year":"2009","unstructured":"Chandran U, Zhao D (2009) SS-KTC: a high-testability low-overhead scan architecture with multi-level security integration. In: Proceedings of VLSI test symposium, pp 321\u2013326"},{"key":"1857_CR22","first-page":"60","volume":"33","author":"M Razzaq","year":"2011","unstructured":"Razzaq M, Singh V, Singh A (2011) SSKTR: secure and testable scan design through test key randomization. Proc Asian Test Symp 33:60\u201365","journal-title":"Proc Asian Test Symp"},{"key":"1857_CR23","first-page":"348","volume-title":"Proceedings of the 14th Asian Test Symposium","author":"D Mukhopadhyay","year":"2005","unstructured":"Mukhopadhyay D, Banerjee S, RoyChowdhury D, Bhattacharya BB (2005) CryptoScan ASecured scan chain architecture. In: Proceedings of the 14th Asian Test Symposium, pp 348\u2013353"},{"key":"1857_CR24","doi-asserted-by":"publisher","first-page":"301","DOI":"10.1007\/s10836-006-7720-x","volume":"22","author":"F Novak","year":"2006","unstructured":"Novak F, Biasizzo A (2006) Security extension for IEEE std 1149.1. J Electron Test 22:301\u2013303","journal-title":"J Electron Test"},{"key":"1857_CR25","doi-asserted-by":"publisher","first-page":"174","DOI":"10.1016\/j.procs.2017.09.123","volume":"115","author":"MI Shiny","year":"2017","unstructured":"Shiny MI, Nirmala DM (2017) LFSR based secured scan design testability techniques. Proc Comput Sci 115:174\u2013181","journal-title":"Proc Comput Sci"},{"key":"1857_CR26","first-page":"36","volume":"1","author":"KV Kumar","year":"2020","unstructured":"Kumar KV, Jayasankar T, Eswaramoorthy V, Nivedhitha V (2020) SDARP: security based data aware routing protocol for ad hoc sensor networks. Int J Intel Netw 1:36\u201342","journal-title":"Int J Intel Netw"},{"issue":"9","key":"1857_CR27","doi-asserted-by":"publisher","first-page":"1867","DOI":"10.1109\/TCAD.2017.2772817","volume":"37","author":"X Wang","year":"2018","unstructured":"Wang X, Zhang D, He M, Su D, Tehranipoor M (2018) Secure scan and test using obfuscation throughout supply chain. IEEE Trans Comput- Aided Design Integr Circuits Syst 37(9):1867\u20131880","journal-title":"IEEE Trans Comput- Aided Design Integr Circuits Syst"},{"key":"1857_CR28","doi-asserted-by":"publisher","first-page":"1752","DOI":"10.3390\/s19081752","volume":"Vol","author":"W Wang","year":"2019","unstructured":"Wang W, Deng Z, Wang J (2019) Enhancing sensor network security with improved internal hardware design. J Sensors Vol:1752","journal-title":"J Sensors"},{"key":"1857_CR29","first-page":"1","volume-title":"Proc. IEEE Int. Symp. Circuits Syst. (ISCAS)","author":"D Vaghani","year":"2018","unstructured":"Vaghani D, Ahlawat S, Tudu J, Fujita M, Singh V (2018) On securing scan design through test vector encryption. In: Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), pp 1\u20135"},{"key":"1857_CR30","first-page":"85","volume":"1","author":"MA Saleem","year":"2020","unstructured":"Saleem MA, Bhardwaj R, Datta D (2020) Application of intelligent computing to develop performance index algorithm as a multicriteria decision making tool. Int J Intel Netw 1:85\u201391","journal-title":"Int J Intel Netw"},{"key":"1857_CR31","first-page":"486","volume-title":"Proceedings of IEEE New Circuits and Systems Conference (NEWCAS)","author":"D Hely","year":"2011","unstructured":"Hely D, Rosenfeld K, Karri R (2011) Security challenges during VLSI test. In: Proceedings of IEEE New Circuits and Systems Conference (NEWCAS), pp 486\u2013489"},{"issue":"4","key":"1857_CR32","first-page":"1","volume":"1","author":"G Daniel","year":"2017","unstructured":"Daniel G, Costa SF, Oliveira G (2017) cryptography in wireless multimedia sensor networks: a survey and research directions. J Crypto 1(4):1\u201318","journal-title":"J Crypto"},{"key":"1857_CR33","first-page":"474","volume-title":"Proceedings of the IEEE International Conference on Communication and Signal Processing (ICCSP), April","author":"M Remy","year":"2014","unstructured":"Remy M, Prabhu E, Mangalam H (2014) A versatile low power Design of bit-Serial Multiplier in finite fields GF (2m). In: Proceedings of the IEEE International Conference on Communication and Signal Processing (ICCSP), April, pp 474\u2013478"}],"container-title":["Mobile Networks and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11036-021-01857-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11036-021-01857-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11036-021-01857-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,16]],"date-time":"2022-07-16T14:12:13Z","timestamp":1657980733000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11036-021-01857-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,2,17]]},"references-count":33,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2022,6]]}},"alternative-id":["1857"],"URL":"https:\/\/doi.org\/10.1007\/s11036-021-01857-8","relation":{},"ISSN":["1383-469X","1572-8153"],"issn-type":[{"value":"1383-469X","type":"print"},{"value":"1572-8153","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,2,17]]},"assertion":[{"value":"3 September 2021","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 February 2022","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}