{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,24]],"date-time":"2026-04-24T11:38:09Z","timestamp":1777030689374,"version":"3.51.4"},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"8","license":[{"start":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T00:00:00Z","timestamp":1691971200000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T00:00:00Z","timestamp":1691971200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Multimed Tools Appl"],"DOI":"10.1007\/s11042-023-16403-9","type":"journal-article","created":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T13:02:10Z","timestamp":1692018130000},"page":"23297-23309","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["High-speed low power energy efficient 1- trit multiplier with less number of CNTFETs"],"prefix":"10.1007","volume":"83","author":[{"given":"Sarada","family":"Musala","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ramana Murthy","family":"Gajula","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"S. V. Raghu Sekhar","family":"Reddy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"P. Prakash","family":"Reddy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2023,8,14]]},"reference":[{"key":"16403_CR1","doi-asserted-by":"publisher","first-page":"56726","DOI":"10.1109\/ACCESS.2021.3072567","volume":"9","author":"JM Aljaam","year":"2021","unstructured":"Aljaam JM, Jaber RA, Al-Maadeed SA (2021) Novel ternary adder and multiplier designs without using decoders or encoders. IEEE Access 9:56726\u201356735. https:\/\/doi.org\/10.1109\/ACCESS.2021.3072567","journal-title":"IEEE Access"},{"issue":"5545","key":"16403_CR2","doi-asserted-by":"publisher","first-page":"1317","DOI":"10.1126\/science.1065824","volume":"294","author":"A Bachtold","year":"2001","unstructured":"Bachtold A, Hadley P, Nakanishi T, Dekker C (2001) Logic circuits with carbon nanotube transistors. Science 294(5545):1317\u20131320","journal-title":"Science"},{"key":"16403_CR3","first-page":"909","volume-title":"Proc IEEE international instrumentation and measurement technology conference, 5\u20137","author":"G Cho","year":"2009","unstructured":"Cho G, Kim YB, Lombardi F, Choi M (2009) Performance evaluation of CNFET-based logic gates. In: Proc IEEE international instrumentation and measurement technology conference, 5\u20137, pp 909\u2013912"},{"key":"16403_CR4","first-page":"1","volume-title":"2018 international symposium on devices, circuits and systems (ISDCS)","author":"D Das","year":"2018","unstructured":"Das D, Banerjee A, Prasad V (2018) Design of ternary logic circuits using CNTFET. In: 2018 international symposium on devices, circuits and systems (ISDCS). IEEE, pp 1\u20136"},{"key":"16403_CR5","doi-asserted-by":"crossref","unstructured":"Doaa K, Abdelrahman RM, Mohammed Fouda E (2020) Comparative study of CNTFET implementations of 1-trit multiplier, Cairo University, Internation Conference on Microelectronics 19(2): 159-256","DOI":"10.1109\/ICM50269.2020.9331789"},{"issue":"93","key":"16403_CR6","first-page":"871","volume":"7","author":"RA Jaber","year":"2019","unstructured":"Jaber RA, Kassem A, El-Hajj AM, El-Nimri LA, Haidar AM (2019) High-performance and energy-efficient cnfet-based designs for ternary logic circuits. IEEE Access 7(93):871\u201393 886","journal-title":"IEEE Access"},{"key":"16403_CR7","first-page":"131","volume-title":"IEEE\/ACM international symposium on nanoscale architectures","author":"J Liang","year":"2012","unstructured":"Liang J, Chen L, Han J, Lombardi F (2012) Design and reliability analysis of multiple valued logic gates using carbon nanotube FETs. In: IEEE\/ACM international symposium on nanoscale architectures. The Netherlands, Amsterdam, pp 131\u2013138"},{"issue":"2","key":"16403_CR8","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/TNANO.2009.2036845","volume":"10","author":"S Lin","year":"2009","unstructured":"Lin S, Kim YB, Lombardi F (2009) CNTFET-based design of ternary logic gates and arithmetic circuits. IEEE Trans Nanotechnol 10(2):217\u2013225","journal-title":"IEEE Trans Nanotechnol"},{"key":"16403_CR9","first-page":"435","volume-title":"Proc. IEEE int. midwest symp. circuits syst","author":"S Lin","year":"2009","unstructured":"Lin S, Kim YB, Lombardi F (2009) A novel CNTFET-based ternarylogic gate design. In: Proc. IEEE int. midwest symp. circuits syst, pp 435\u2013438"},{"issue":"1","key":"16403_CR10","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1109\/TNANO.2002.1005429","volume":"1","author":"PL McEuen","year":"2002","unstructured":"McEuen PL, Fuhrer M, Park H (2002) Single-walled carbon nanotube electronics. IEEE Trans Nanotechnol 1(1):78\u201385","journal-title":"IEEE Trans Nanotechnol"},{"key":"16403_CR11","doi-asserted-by":"crossref","unstructured":"Nepal K (2010) Dynamic circuits for ternary computation in carbon nanotube-based field effect transistors, NEWCAS conference (NEWCAS), 2010 8th IEEE international, pp 53-56: 20-23","DOI":"10.1109\/NEWCAS.2010.5603726"},{"issue":"12","key":"16403_CR12","doi-asserted-by":"publisher","first-page":"3195","DOI":"10.1109\/TCSI.2013.2264694","volume":"60","author":"J-S Pan","year":"2013","unstructured":"Pan J-S, Lee C-Y, Meher PK (2013) Low-latency digit-serial and digit-parallel systolic multipliers for large binary extension fields. IEEE Trans Circuits Syst I: Regul Pap 60(12):3195\u20133204. https:\/\/doi.org\/10.1109\/TCSI.2013.2264694","journal-title":"IEEE Trans Circuits Syst I: Regul Pap"},{"issue":"7","key":"16403_CR13","doi-asserted-by":"publisher","first-page":"1614","DOI":"10.1109\/TVLSI.2019.2903289","volume":"27","author":"J-S Pan","year":"2019","unstructured":"Pan J-S, Lee C-Y, Sghaier A, Zeghid M, Xie J (2019) Novel systolization of subquadratic space complexity multipliers based on Toeplitz matrix\u2013vector product approach. IEEE Trans Very Large Scale Integr (VLSI) Syst 27(7):1614\u20131622. https:\/\/doi.org\/10.1109\/TVLSI.2019.2903289","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"issue":"2","key":"16403_CR14","doi-asserted-by":"publisher","first-page":"168","DOI":"10.1109\/TNANO.2004.842068","volume":"4","author":"A Ray chowdhury","year":"2005","unstructured":"Ray chowdhury A, Roy K (2005) Carbon-nanotube-based voltage-mode multiple valued logic design. IEEE Trans Nanotechnol 4(2):168\u2013179","journal-title":"IEEE Trans Nanotechnol"},{"issue":"3","key":"16403_CR15","doi-asserted-by":"publisher","first-page":"423","DOI":"10.1631\/FITEE.1500366","volume":"18","author":"S Tabrizchi","year":"2017","unstructured":"Tabrizchi S, Azimi N, Navi K (2017) A novel ternary half adder and multiplier based on carbon nanotube field effect transistors. Front Inf Technol Electron Eng 18(3):423\u2013433","journal-title":"Front Inf Technol Electron Eng"},{"key":"16403_CR16","first-page":"8887","volume":"975","author":"H Vani","year":"2015","unstructured":"Vani H, Sagar R, Rohini H (2015) Multiplexer based design for ternary logic circuits. Int J Comput Appl 975:8887","journal-title":"Int J Comput Appl"},{"key":"16403_CR17","doi-asserted-by":"crossref","unstructured":"Vudadha C, Sreehari V Srinivas MB (2012) Multiplexer based design for ternary logic circuits, PRIME 2012, Aachen, Germany Session TG1 \u2013 Analog and Mixed Signal III, pp 139-142","DOI":"10.1109\/FTFC.2012.6231748"},{"key":"16403_CR18","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1109\/PrimeAsia.2013.6731176","volume-title":"2013 IEEE Asia Pacific conference on postgraduate research in microelectronics and electronics (PrimeAsia)","author":"C Vudadha","year":"2013","unstructured":"Vudadha C, Katragadda S, Phaneendra PS (2013) 2: 1 multiplexer-based design for ternary logic circuits. In: 2013 IEEE Asia Pacific conference on postgraduate research in microelectronics and electronics (PrimeAsia). IEEE, pp 46\u201351"}],"container-title":["Multimedia Tools and Applications"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11042-023-16403-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11042-023-16403-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11042-023-16403-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,26]],"date-time":"2024-10-26T04:03:27Z","timestamp":1729915407000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11042-023-16403-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8,14]]},"references-count":18,"journal-issue":{"issue":"8","published-online":{"date-parts":[[2024,3]]}},"alternative-id":["16403"],"URL":"https:\/\/doi.org\/10.1007\/s11042-023-16403-9","relation":{},"ISSN":["1573-7721"],"issn-type":[{"value":"1573-7721","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,8,14]]},"assertion":[{"value":"21 February 2022","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 May 2023","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 July 2023","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 August 2023","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare that we have no conflict of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}