{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T07:39:16Z","timestamp":1740123556870,"version":"3.37.3"},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2018,3,10]],"date-time":"2018-03-10T00:00:00Z","timestamp":1520640000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Multidim Syst Sign Process"],"published-print":{"date-parts":[[2019,1]]},"DOI":"10.1007\/s11045-018-0559-3","type":"journal-article","created":{"date-parts":[[2018,3,9]],"date-time":"2018-03-09T21:09:38Z","timestamp":1520629778000},"page":"343-361","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Convergent method for designing high-accuracy bi-equiripple variable-delay filters using new delay-error expression"],"prefix":"10.1007","volume":"30","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8501-9151","authenticated-orcid":false,"given":"Tian-Bo","family":"Deng","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,3,10]]},"reference":[{"issue":"6","key":"559_CR1","doi-asserted-by":"publisher","first-page":"637","DOI":"10.1109\/82.943337","volume":"48","author":"T-B Deng","year":"2001","unstructured":"Deng, T.-B. (2001). Discretization-free design of variable fractional-delay FIR digital filters. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 48(6), 637\u2013644.","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"6","key":"559_CR2","doi-asserted-by":"publisher","first-page":"1668","DOI":"10.1109\/TSP.2004.827150","volume":"52","author":"T-B Deng","year":"2004","unstructured":"Deng, T.-B. (2004). Closed-form design and efficient implementation of variable digital filters with simultaneously tunable magnitude and fractional-delay. IEEE Transactions on Signal Processing, 52(6), 1668\u20131681.","journal-title":"IEEE Transactions on Signal Processing"},{"issue":"12","key":"559_CR3","doi-asserted-by":"publisher","first-page":"2718","DOI":"10.1109\/TCSI.2007.905649","volume":"54","author":"T-B Deng","year":"2007","unstructured":"Deng, T.-B. (2007). Symmetric structures for odd-order maximally flat and weighted-least-squares variable fractional-delay filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 54(12), 2718\u20132732.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"10","key":"559_CR4","doi-asserted-by":"publisher","first-page":"692","DOI":"10.1109\/TCSII.2011.2164160","volume":"58","author":"T-B Deng","year":"2011","unstructured":"Deng, T.-B. (2011). Minimax design of low-complexity even-order variable fractional-delay filters using second-order cone programming. IEEE Transactions on Circuits and Systems II: Express Briefs, 58(10), 692\u2013696.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"559_CR5","doi-asserted-by":"crossref","unstructured":"Deng, T.-B. (2012a). Bi-minimax design of odd-order variable fractional-delay digital filters. In Proceedings of IEEE ISCAS 2012 (pp. 786\u2013789) Seoul, Korea.","DOI":"10.1109\/ISCAS.2012.6272157"},{"key":"559_CR6","doi-asserted-by":"crossref","unstructured":"Deng, T.-B. (2012b). Low-complexity and high-accuracy odd-order variable fractional-delay digital filters. In Proceedings of IEEE ICASSP 2012 (pp. 1589\u20131592). Kyoto, Japan.","DOI":"10.1109\/ICASSP.2012.6288197"},{"issue":"8","key":"559_CR7","doi-asserted-by":"publisher","first-page":"1766","DOI":"10.1109\/TCSI.2011.2180431","volume":"59","author":"T-B Deng","year":"2012","unstructured":"Deng, T.-B., Chivapreecha, S., & Dejhan, K. (2012). Bi-minimax design of even-order variable fractional-delay FIR digital filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(8), 1766\u20131774.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"8","key":"559_CR8","doi-asserted-by":"publisher","first-page":"3023","DOI":"10.1109\/TSP.2006.875385","volume":"54","author":"T-B Deng","year":"2006","unstructured":"Deng, T.-B., & Lian, Y. (2006). Weighted-least-squares design of variable fractional-delay FIR filters using coefficient-symmetry. IEEE Transactions on Signal Processing, 54(8), 3023\u20133038.","journal-title":"IEEE Transactions on Signal Processing"},{"issue":"4","key":"559_CR9","doi-asserted-by":"publisher","first-page":"923","DOI":"10.1016\/j.sigpro.2012.11.004","volume":"93","author":"T-B Deng","year":"2013","unstructured":"Deng, T.-B., & Qin, W. (2013). Coefficient relation-based minimax design and low-complexity structure of variable fractional-delay digital filters. Signal Processing, 93(4), 923\u2013932.","journal-title":"Signal Processing"},{"issue":"1","key":"559_CR10","doi-asserted-by":"publisher","first-page":"300","DOI":"10.1016\/j.sigpro.2013.07.004","volume":"94","author":"T-B Deng","year":"2014","unstructured":"Deng, T.-B., & Qin, W. (2014). Improved bi-equiripple variable fractional-delay filters. Signal Processing, 94(1), 300\u2013307.","journal-title":"Signal Processing"},{"issue":"3","key":"559_CR11","doi-asserted-by":"publisher","first-page":"438","DOI":"10.1016\/j.sigpro.2015.10.002","volume":"120","author":"T-B Deng","year":"2016","unstructured":"Deng, T.-B., & Soontornwong, P. (2016). Delay-error-constrained minimax design of all-pass variable-fractional-delay digital filters. Signal Processing, 120(3), 438\u2013447.","journal-title":"Signal Processing"},{"key":"559_CR12","doi-asserted-by":"crossref","unstructured":"Farrow, C. W. (1988). A continuously variable digital delay element. In Proceedings of IEEE ISCAS 1988 (Vol. 3, pp. 2641\u20132645). Espoo, Finland.","DOI":"10.1109\/ISCAS.1988.15483"},{"issue":"2","key":"559_CR13","doi-asserted-by":"publisher","first-page":"123","DOI":"10.1109\/82.205818","volume":"39","author":"G-S Liu","year":"1992","unstructured":"Liu, G.-S., & Wei, C.-W. (1992). A new variable fractional sample delay filter with nonlinear interpolation. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 39(2), 123\u2013126.","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"2","key":"559_CR14","doi-asserted-by":"publisher","first-page":"66","DOI":"10.1049\/iet-spr:20060260","volume":"1","author":"J-C Liu","year":"2007","unstructured":"Liu, J.-C., & You, S.-J. (2007). Weighted least squares near-equiripple approximation of variable fractional delay FIR filters. IET Signal Processing, 1(2), 66\u201372.","journal-title":"IET Signal Processing"},{"issue":"5","key":"559_CR15","doi-asserted-by":"publisher","first-page":"989","DOI":"10.1109\/TCSI.2012.2188945","volume":"59","author":"S-C Pei","year":"2012","unstructured":"Pei, S.-C., Shyu, J.-J., Huang, Y.-D., & Chan, C.-H. (2012). Improved methods for the design of variable fractional-delay IIR digital filters. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(5), 989\u20131000.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"4","key":"559_CR16","doi-asserted-by":"publisher","first-page":"1002","DOI":"10.13164\/re.2015.1002","volume":"24","author":"P Soontornwong","year":"2015","unstructured":"Soontornwong, P., & Chivapreecha, S. (2015). Pascal-interpolation-based noninteger delay filter and low-complexity realization. Radioengineering, 24(4), 1002\u20131012.","journal-title":"Radioengineering"},{"issue":"7","key":"559_CR17","doi-asserted-by":"publisher","first-page":"1458","DOI":"10.1109\/TCSI.2011.2177136","volume":"59","author":"C-C Tseng","year":"2012","unstructured":"Tseng, C.-C., & Lee, S.-L. (2012). Design of fractional delay filter using Hermite interpolation method. IEEE Transactions on Circuits and Systems I: Regular Papers, 59(7), 1458\u20131471.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"}],"container-title":["Multidimensional Systems and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11045-018-0559-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11045-018-0559-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11045-018-0559-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,3,9]],"date-time":"2019-03-09T19:19:08Z","timestamp":1552159148000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11045-018-0559-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3,10]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2019,1]]}},"alternative-id":["559"],"URL":"https:\/\/doi.org\/10.1007\/s11045-018-0559-3","relation":{},"ISSN":["0923-6082","1573-0824"],"issn-type":[{"type":"print","value":"0923-6082"},{"type":"electronic","value":"1573-0824"}],"subject":[],"published":{"date-parts":[[2018,3,10]]},"assertion":[{"value":"18 January 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"7 October 2017","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 February 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"10 March 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}