{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,15]],"date-time":"2026-01-15T07:45:38Z","timestamp":1768463138001,"version":"3.49.0"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2021,3,15]],"date-time":"2021-03-15T00:00:00Z","timestamp":1615766400000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,3,15]],"date-time":"2021-03-15T00:00:00Z","timestamp":1615766400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Multidim Syst Sign Process"],"published-print":{"date-parts":[[2021,7]]},"DOI":"10.1007\/s11045-021-00772-1","type":"journal-article","created":{"date-parts":[[2021,3,15]],"date-time":"2021-03-15T16:03:39Z","timestamp":1615824219000},"page":"1041-1063","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":25,"title":["A novel parallel prefix adder for optimized Radix-2 FFT processor"],"prefix":"10.1007","volume":"32","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4240-2177","authenticated-orcid":false,"given":"Garima","family":"Thakur","sequence":"first","affiliation":[]},{"given":"Harsh","family":"Sohal","sequence":"additional","affiliation":[]},{"given":"Shruti","family":"Jain","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,3,15]]},"reference":[{"key":"772_CR1","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1016\/j.tcs.2018.06.007","volume":"773","author":"EPA Akbar","year":"2019","unstructured":"Akbar, E. P. A., & Mosleh, M. (2019). An efficient design for reversible wallace unsigned multiplier. Theoretical Computer Science, 773, 43\u201352.","journal-title":"Theoretical Computer Science"},{"key":"772_CR2","doi-asserted-by":"crossref","unstructured":"Akhil, R., Koleti, J. R., Vijaya Bhaskar, A., Sathish, V., & Goud, B. A. (2020). Delay and area analysis of hardware implementation of FFT using FPGA. In: IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT): 1\u20136.","DOI":"10.1109\/CONECCT50063.2020.9198617"},{"issue":"3","key":"772_CR3","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1109\/TC.1982.1675982","volume":"31","author":"RP Brent","year":"1982","unstructured":"Brent, R. P., & Kung, H. T. (1982). A regular layout for parallel adders. IEEE Transactions on Computers, 31(3), 260\u2013264.","journal-title":"IEEE Transactions on Computers"},{"issue":"2","key":"772_CR4","doi-asserted-by":"publisher","first-page":"221","DOI":"10.1109\/TVLSI.2014.2304834","volume":"23","author":"J Chen","year":"2015","unstructured":"Chen, J., Hu, J., Lee, S., & Sobelman, G. E. (2015). Hardware Efficient Mixed Radix-25\/16\/9 FFT for LTE Systems. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 23(2), 221\u2013229.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"2","key":"772_CR5","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1109\/TC.2005.26","volume":"54","author":"G Dimitrakopoulos","year":"2005","unstructured":"Dimitrakopoulos, G., & Nikolos, D. (2005). high-speed parallel-prefix VLSI ling adders. IEEE Transactions on Computers, 54(2), 225\u2013231.","journal-title":"IEEE Transactions on Computers"},{"key":"772_CR6","doi-asserted-by":"crossref","unstructured":"Hans, T., & Carlson, D. A. (1987). Fast area-Eeficient VLSI adders. In: Proc. 8th IEEE Symposius on Computer Arithmetic, pp 49\u201356.","DOI":"10.1109\/ARITH.1987.6158699"},{"key":"772_CR7","doi-asserted-by":"crossref","unstructured":"Hussain, I., Pandey, C. K., & Chaudhury, S. (2019). Design and analysis of high performance multiplier circuit. Devices for Integrated Circuit (DevIC): 23\u201324.","DOI":"10.1109\/DEVIC.2019.8783322"},{"key":"772_CR8","first-page":"45","volume":"9","author":"D Jayakumar","year":"2016","unstructured":"Jayakumar, D., & Logashanmugam, E. (2016). Design of combined Radix-2, Radix-4 and Radix-8 based single path delay feedback (SDF) FFT. Indian journal of science and technology, 9, 45.","journal-title":"Indian journal of science and technology"},{"key":"772_CR9","unstructured":"Kavya, T., Deepa, K., & Jayamangala, S. (2017). Design and implementation of high performance Radix-2 and Radix-4 butterflies from FFT. International Journal of Electronics, Electrical and Computational System, 6(12), 363\u2013367."},{"issue":"8","key":"772_CR10","doi-asserted-by":"publisher","first-page":"786","DOI":"10.1109\/TC.1973.5009159","volume":"22","author":"PM Kogge","year":"1973","unstructured":"Kogge, P. M., & Stone, H. S. (1973). A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, 22(8), 786\u2013793.","journal-title":"IEEE Transactions on Computers"},{"issue":"4","key":"772_CR11","doi-asserted-by":"publisher","first-page":"831","DOI":"10.1145\/322217.322232","volume":"27","author":"RE Ladner","year":"1980","unstructured":"Ladner, R. E., & Fisher, M. J. (1980). Parallel Prefix Computation. Journal of the AssoclaUon for Computing Machinery, 27(4), 831\u2013838.","journal-title":"Journal of the AssoclaUon for Computing Machinery"},{"issue":"3","key":"772_CR12","doi-asserted-by":"publisher","first-page":"511","DOI":"10.1109\/TVLSI.2018.2879675","volume":"27","author":"S Liu","year":"2019","unstructured":"Liu, S., & Liu, D. (2019). A High-Flexible Low-Latency Memory-Based FFT Processor for 4G, WLAN, and Future 5G. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 27(3), 511\u2013523.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"772_CR13","unstructured":"Narvekar, N. Raikar, S., Salkar, P., & Shirodkar, A. (2019). Implementation of FFT processor on FPGA using Vedic multiplier. International journal of research and analytical reviews, 6(2), 211\u2013215."},{"key":"772_CR14","doi-asserted-by":"crossref","unstructured":"Santhosh, L., & Thomas A. (2013). Implementation of Radix 2 and Radix 22 FFT algorithms on Spartan 6 FPGA. In: International Conference on Computer Communication and Networking.","DOI":"10.1109\/ICCCNT.2013.6726840"},{"issue":"1","key":"772_CR15","doi-asserted-by":"publisher","first-page":"118","DOI":"10.1109\/TCSI.2017.2725338","volume":"65","author":"X Shih","year":"2018","unstructured":"Shih, X., Chou, H., & Liu, Y. (2018). VLSI Design and Implementation of Reconfigurable 46-Mode Combined-Radix-Based FFT Hardware Architecture for 3GPP-LTE Applications. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(1), 118\u2013129.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"key":"772_CR16","doi-asserted-by":"crossref","unstructured":"Singh, A. K., & Nandi, A. (2017). Design of Radix 2 butterfly structure using Vedic multiplier and CLA on Xilinx. In: Proc. IEEE Conference on Emerging Devices and Smart Systems.","DOI":"10.1109\/ICEDSS.2017.8073670"},{"issue":"12","key":"772_CR17","doi-asserted-by":"publisher","first-page":"3394","DOI":"10.1109\/TCSI.2014.2327315","volume":"61","author":"S Tang","year":"2014","unstructured":"Tang, S., Jan, F., Cheng, H., Lin, C., & Wu, G. (2014). Multimode memory-based FFT processor for wireless display FD-OCT medical systems. IEEE Transactions on Circuits and Systems I: Regular Papers, 61(12), 3394\u20133406.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"7","key":"772_CR18","first-page":"340","volume":"5","author":"G Thakur","year":"2018","unstructured":"Thakur, G., Sohal, H., & Jain, S. (2018a). Design and comparative performance analysis of various multiplier circuit. Journal of Scientific and Engineering Research, 5(7), 340\u2013434.","journal-title":"Journal of Scientific and Engineering Research"},{"issue":"7","key":"772_CR19","first-page":"340","volume":"5","author":"G Thakur","year":"2018","unstructured":"Thakur, G., Sohal, H., & Jain, S. (2018b). An efficient design of 8-bit high speed parallel prefix adder. Research Journal of Science and Technology, 5(7), 340\u2013349.","journal-title":"Research Journal of Science and Technology"},{"issue":"3.4","key":"772_CR20","doi-asserted-by":"publisher","first-page":"213","DOI":"10.14419\/ijet.v7i3.4.16777","volume":"7","author":"G Thakur","year":"2018","unstructured":"Thakur, G., Sohal, H., & Jain, S. (2018c). High speed RADIX-2 butterfly structure using novel Wallace multiplier. International Journal of Engineering & Technology, 7(3.4), 213\u2013217.","journal-title":"International Journal of Engineering & Technology"},{"key":"772_CR21","doi-asserted-by":"crossref","unstructured":"Thakur, G., Sohal, H., & Jain, S. (2020a). Design and analysis of high-speed parallel prefix adder for digital circuit design applications. In: International Conference on Computational Performance Evaluation (ComPE), pp 095\u2013100.","DOI":"10.1109\/ComPE49325.2020.9200064"},{"key":"772_CR22","doi-asserted-by":"crossref","unstructured":"Thakur, G., Sohal, H., & Jain, S. (2020b). FPGA-based parallel prefix speculative adder for fast computation application. In: 2020 Sixth International Conference on Parallel, Distributed and Grid Computing (PDGC), pp. 206\u2013210.","DOI":"10.1109\/PDGC50313.2020.9315783"},{"issue":"1","key":"772_CR23","doi-asserted-by":"publisher","first-page":"14","DOI":"10.1109\/PGEC.1964.263830","volume":"13","author":"CS Wallace","year":"1964","unstructured":"Wallace, C. S. (1964). A Suggestion for a Fast Multiplier. IEEE Transactions on Electronic Computers, 13(1), 14\u201317.","journal-title":"IEEE Transactions on Electronic Computers"},{"issue":"8","key":"772_CR24","doi-asserted-by":"publisher","first-page":"1134","DOI":"10.1109\/TC.2010.103","volume":"59","author":"RS Water","year":"2010","unstructured":"Water, R. S., & Swartzlander, E. E. (2010). A Reduced complexity wallace multiplier reduction. IEEE Transactions on Computers, 59(8), 1134\u20131137.","journal-title":"IEEE Transactions on Computers"}],"container-title":["Multidimensional Systems and Signal Processing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11045-021-00772-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11045-021-00772-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11045-021-00772-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2021,6,5]],"date-time":"2021-06-05T21:05:47Z","timestamp":1622927147000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11045-021-00772-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,3,15]]},"references-count":24,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2021,7]]}},"alternative-id":["772"],"URL":"https:\/\/doi.org\/10.1007\/s11045-021-00772-1","relation":{},"ISSN":["0923-6082","1573-0824"],"issn-type":[{"value":"0923-6082","type":"print"},{"value":"1573-0824","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,3,15]]},"assertion":[{"value":"20 July 2020","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 February 2021","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"22 February 2021","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 March 2021","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}