{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,22]],"date-time":"2025-08-22T04:46:36Z","timestamp":1755837996942},"reference-count":13,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2005,6,1]],"date-time":"2005-06-01T00:00:00Z","timestamp":1117584000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2005,6]]},"DOI":"10.1007\/s11227-005-0160-z","type":"journal-article","created":{"date-parts":[[2005,3,4]],"date-time":"2005-03-04T12:31:30Z","timestamp":1109939490000},"page":"217-229","source":"Crossref","is-referenced-by-count":22,"title":["Parallel Queue Processor Architecture Based on Produced Order Computation Model"],"prefix":"10.1007","volume":"32","author":[{"given":"Masahiro","family":"Sowa","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ben A.","family":"Abderazek","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tsutomu","family":"Yoshinaga","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","reference":[{"key":"CR1","unstructured":"B. A. Abderazek, M. Arsenji, K. Kiuchi, M. Akanda, S. Shigeta, T. Yoshinaga, and M. Sowa. PQPpfB: Parallel queue processor architecture in verilog-HDL. IPSJ, 66th Conference, 2004."},{"key":"CR2","unstructured":"B. A. Abderazek, N. Kirilka, and M. Sowa. FARM-queue mode: On a practical queue execution model. In Proceedings of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, Japan, pp. 939?944,2001."},{"key":"CR3","doi-asserted-by":"crossref","unstructured":"S. Aditya, B. R. Rau, and V. Kathail. Automatic architectural synthesis of VLIW and EPIC processors. In Proc. 12th Int?l Symp. System Synthesis. IEEE CS Press, Los Alamitos, Calif., pp. 107?113, 1999.","DOI":"10.1109\/ISSS.1999.814268"},{"key":"CR4","doi-asserted-by":"crossref","unstructured":"R. Bruno and V. Carla. Data flow on queue machines. In 12th Int. IEEE Symposium on Computer Architecture, pp. 342?351, 1985.","DOI":"10.1145\/327070.327367"},{"issue":"8","key":"CR5","doi-asserted-by":"crossref","first-page":"967","DOI":"10.1109\/12.2247","volume":"37","author":"R. P. Colwell","year":"1988","unstructured":"R. P. Colwell, R. P. Nix, J. J. O?Donnel, D. P. Papworth, and P. K. Rodman, A VLIW architecture for a trace scheduling compiler. IEEE Computer Transaction, 37(8):967?979, 1988.","journal-title":"IEEE Computer Transaction"},{"issue":"8","key":"CR6","doi-asserted-by":"crossref","first-page":"814","DOI":"10.1109\/12.868027","volume":"49","author":"T. Conte","year":"2002","unstructured":"T. Conte and S. Sathaye, Properties of rescheduling size invariance for dynamic rescheduling-based VLIW cross-generation compatibility. IEEE Computer Transaction, 49(8):814?825, 2002.","journal-title":"IEEE Computer Transaction"},{"key":"CR7","unstructured":"S. Okamoto, H. Suzuki, A. Maeda, and M. Sowa. Design of a Superscalar Processor Based on Queue Machine Computation Model: IEEE PACRIM, pp. 22?24, 1999."},{"issue":"81","key":"CR8","first-page":"127","volume":"2","author":"Y. Okumura","year":"2002","unstructured":"Y. Okumura, T. Yoshinaga and M. Sowa. Parallel C compiler for queue machines. In IPSJ Symposium for Computer Architecture, 2(81):127?132, 2002.","journal-title":"IPSJ Symposium for Computer Architecture"},{"key":"CR9","unstructured":"S. Palacharia, N. P Joupi, and J.E. Smith. Complexity-effective super-scalar processor. Ph.D. dissertation, Univ. of Wisconsin, 1998."},{"key":"CR10","doi-asserted-by":"crossref","unstructured":"R. Radhakrishnan, D. Talla, and L. K. John. Allowing for ILP in an embedded Java processor. In Proceedings of IEEE\/ACM International Symposium on Computer Architecture, Vancouver, CA, pp. 294?305,2000.","DOI":"10.1145\/339647.339702"},{"issue":"2","key":"CR11","doi-asserted-by":"crossref","first-page":"37","DOI":"10.1109\/2.820037","volume":"33","author":"M. S. Schlansker","year":"2000","unstructured":"M. S. Schlansker and B. Ramakrishna Rau, EPIC: Explicitly parallel instruction computing. IEEE computer, 33(2):37?45, 2000.","journal-title":"IEEE computer"},{"key":"CR12","unstructured":"M. Sowa, B. A. Abderazek, S. Shigeta, K. Nikolova, and T. Yoshinaga. Proposal and design of a parallel queue processor architecture (PQP). In 14th IASTED Int. Conf. on Parallel and Distributed Computing and System. Cambridge, USA, pp. 554?560, 2002."},{"issue":"21","key":"CR13","first-page":"91","volume":"99","author":"H. Suzuki","year":"1999","unstructured":"H. Suzuki, O. Shusuke, A. Maeda, and M. Sowa. Implementation and evaluation of a superscalar processor based on queue machine computation model. IPSJ SIG, 99(21):91?96, 1999.","journal-title":"IPSJ SIG"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-005-0160-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-005-0160-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-005-0160-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,4,6]],"date-time":"2020-04-06T03:42:12Z","timestamp":1586144532000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-005-0160-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,6]]},"references-count":13,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["160"],"URL":"https:\/\/doi.org\/10.1007\/s11227-005-0160-z","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2005,6]]}}}