{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,29]],"date-time":"2022-03-29T22:11:28Z","timestamp":1648591888731},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2011,8,30]],"date-time":"2011-08-30T00:00:00Z","timestamp":1314662400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2012,9]]},"DOI":"10.1007\/s11227-011-0671-8","type":"journal-article","created":{"date-parts":[[2011,8,29]],"date-time":"2011-08-29T12:59:21Z","timestamp":1314622761000},"page":"1024-1047","source":"Crossref","is-referenced-by-count":1,"title":["Instruction scheduling methods and phase ordering framework for VLIW DSP processors with distributed register files"],"prefix":"10.1007","volume":"61","author":[{"given":"Chung-Ju","family":"Wu","sequence":"first","affiliation":[]},{"given":"Yu-Te","family":"Lin","sequence":"additional","affiliation":[]},{"given":"Jenq-Kuen","family":"Lee","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2011,8,30]]},"reference":[{"key":"671_CR1","doi-asserted-by":"crossref","first-page":"292","DOI":"10.1109\/MICRO.1992.697033","volume-title":"Proceedings of the 25th annual international symposium on microarchitecture","author":"A Capitanio","year":"1992","unstructured":"Capitanio A, Dutt N, Nicolau A (1992) Partitioned register files for VLIW\u2019s: a preliminary analysis of tradeoffs. In: Proceedings of the 25th annual international symposium on microarchitecture, December, pp 292\u2013300"},{"key":"671_CR2","unstructured":"Texas Instruments (2000) TMS320C64x technical overview. Texas Instruments, Feb"},{"key":"671_CR3","unstructured":"CEVA (2004) CEVA-X1620 datasheet. CEVA"},{"key":"671_CR4","unstructured":"Chang D, Baron M (2004) Taiwan\u2019s roadmap to leadership in design. Microprocessor Report, In-Stat\/MDR, December"},{"key":"671_CR5","first-page":"291","volume-title":"Proceedings of international conference on parallel architecture and compilation techniques","author":"R Leupers","year":"2000","unstructured":"Leupers R (2000) Instruction scheduling for clustered VLIW DSPs. In: Proceedings of international conference on parallel architecture and compilation techniques, October, pp 291\u2013300"},{"key":"671_CR6","volume-title":"International conference on parallel architectures and compilation techniques","author":"Y Qian","year":"2002","unstructured":"Qian Y, Carr S, Sweany PH (2002) Optimizing loop performance for clustered VLIW architectures. In: International conference on parallel architectures and compilation techniques, September"},{"key":"671_CR7","volume-title":"Concurrency and computation: practice and experience","author":"Y-C Lin","year":"2007","unstructured":"Lin Y-C, You Y-P, Lee J-K (2007) PALF: compiler supports for irregular register files in clustered VLIW DSP processors. In: Concurrency and computation: practice and experience"},{"issue":"2","key":"671_CR8","doi-asserted-by":"crossref","first-page":"291","DOI":"10.1002\/j.1538-7305.1970.tb01770.x","volume":"49","author":"BW Kernighan","year":"1970","unstructured":"Kernighan BW, Lin S (1970) An efficient heuristic procedure for partitioning graphs. Bell Syst Tech\u00a0J 49(2):291\u2013307","journal-title":"Bell Syst Tech\u00a0J"},{"key":"671_CR9","doi-asserted-by":"crossref","unstructured":"Pothen A, Simon HD, Liou K-P (1990) Partitioning sparse matrices with eigenvectors of graphs. SIAM J Matrix Anal Appl, July","DOI":"10.1137\/0611030"},{"key":"671_CR10","volume-title":"Proceedings of the 36th annual ACM\/IEEE design automation conference","author":"G Karypis","year":"1999","unstructured":"Karypis G, Kumar V (1999) Multilevel k-way hypergraph partitioning. In: Proceedings of the 36th annual ACM\/IEEE design automation conference"},{"key":"671_CR11","doi-asserted-by":"crossref","unstructured":"Wu C-J, Chen S-Y, Lee J-K (2006) Copy propagation optimizations for vliw dsp processors with distributed register files. Lang Compilers Parallel Comput. doi: 10.1007\/978-3-540-72521-3_19","DOI":"10.1007\/978-3-540-72521-3_19"},{"key":"671_CR12","doi-asserted-by":"crossref","unstructured":"Lu C-H, Lin Y-C, You Y-P, Lee J-K (2008) LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurr Comput Pract Exp. doi: 10.1002\/cpe.v21:1","DOI":"10.1002\/cpe.v21:1"},{"key":"671_CR13","volume-title":"International workshop on compilers for parallel computing","author":"C-J Wu","year":"2009","unstructured":"Wu C-J, Lu C-H, Lee J-J (2009) Expression rematerialization for VLIW DSP processors with distributed register files. In: International workshop on compilers for parallel computing, January"},{"key":"671_CR14","volume-title":"Proceedings of the 21th international conference on computer design","author":"TJ Lin","year":"2003","unstructured":"Lin TJ, Chang CC, Lee CC, Jen CW (2003) An efficient VLIW DSP architecture for baseband processing. In: Proceedings of the 21th international conference on computer design"},{"key":"671_CR15","volume-title":"Proceedings of the 15th ACM Great Lakes symposium on VLSI","author":"T-J Lin","year":"2005","unstructured":"Lin T-J, Chao C-M, Liu C-H, Hsiao P-C, Chen S-K, Lin L-C, Liu C-W, Jen C-W (2005) Computer architecture: a\u00a0unified processor architecture for RISC & VLIW DSP. In: Proceedings of the 15th ACM Great Lakes symposium on VLSI, April"},{"key":"671_CR16","volume-title":"IEEE 4th annual workshop on workload characterization","author":"MR Guthaus","year":"2001","unstructured":"Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) MiBench: a\u00a0free, commercially representative embedded benchmark suite. In: IEEE 4th annual workshop on workload characterization, December"},{"key":"671_CR17","unstructured":"EDN Embedded Microprocessor Benchmark Consortium (2011) http:\/\/www.eembc.org"},{"key":"671_CR18","volume-title":"Software: practice and experience","author":"I Cutcutache","year":"2008","unstructured":"Cutcutache I, Wong W-F (2008) Fast, frequency-based, integrated register allocation and instruction scheduling. In: Software: practice and experience"},{"key":"671_CR19","doi-asserted-by":"crossref","unstructured":"Ivanov DS (2010) Register allocation with instruction scheduling for VLIW-architectures. Program Comput Softw. doi: 10.1134\/S0361768810060058","DOI":"10.1134\/S0361768810060058"},{"key":"671_CR20","doi-asserted-by":"crossref","unstructured":"Kim D-H, Lee H-J (2009) Fine-grain register allocation and instruction scheduling in a reference flow. Comput\u00a0J. doi: 10.1093\/comjnl\/bxp056","DOI":"10.1093\/comjnl\/bxp056"},{"key":"671_CR21","volume-title":"Bulldog: a\u00a0compiler for VLIW architectures","author":"JR Ellis","year":"1986","unstructured":"Ellis JR (1986) Bulldog: a\u00a0compiler for VLIW architectures. MIT Press, Cambridge"},{"key":"671_CR22","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1007\/BF01205182","volume":"7","author":"PG Lowney","year":"1993","unstructured":"Lowney PG, Freudenberger SM, Karzes TJ, Lichtenstein WD, Nix RP, O\u2019Donell JS, Ruttenberf JC (1993) The multiflow trace scheduling compiler. J Supercomput 7:51\u2013142","journal-title":"J Supercomput"},{"key":"671_CR23","unstructured":"Capitanio A, Dutt N, Nicolau A (1993) Design considerations for limited connectivity VLIW architectures. Technical Report, department of information and computer science, University of California, Irvine"},{"key":"671_CR24","volume-title":"Proceedings of the 12th international conference on architectural support for programming languages and operating systems","author":"M Mercaldi","year":"2006","unstructured":"Mercaldi M, Swanson S, Petersen A, Putnam A, Schwerin A, Oskin M, Eggers SJ (2006) Instruction scheduling for a tiled dataflow architecture. In: Proceedings of the 12th international conference on architectural support for programming languages and operating systems"},{"key":"671_CR25","volume-title":"Proceedings of the international symposium on microarchitecture","author":"S Swanson","year":"2003","unstructured":"Swanson S, Michelson K, Schwerin A, Oskin M (2003) WaveScalar. In: Proceedings of the international symposium on microarchitecture"},{"key":"671_CR26","unstructured":"Desoli G (1998) Instruction assignment for clustered VLIW DSP compilers: a\u00a0new approach. Technical Report, Hewlett-Packard Laboratories"},{"key":"671_CR27","volume-title":"Proceedings of the 31st annual international symposium on microarchitecture","author":"E Ozer","year":"1998","unstructured":"Ozer E, Banerjia S, Conte TM (1998) Unified assign and schedule: a\u00a0new approach to scheduling for clustered register files micro architectures. In: Proceedings of the 31st annual international symposium on microarchitecture, November"},{"key":"671_CR28","doi-asserted-by":"crossref","unstructured":"Kirkpatrick S, Gelatt CD, Vecchi MP (1983) Optimization by simulated annealing. Science. doi: 10.1126\/science.220.4598.671","DOI":"10.1126\/science.220.4598.671"},{"key":"671_CR29","doi-asserted-by":"crossref","first-page":"47","DOI":"10.1016\/0096-0551(81)90048-5","volume":"6","author":"GJ Chaitin","year":"1981","unstructured":"Chaitin GJ, Auslander MA, Chandra AK, Cocke J, Hopkins ME, Markstein PW (1981) Register allocation via coloring. Comput Lang 6:47\u201357","journal-title":"Comput Lang"},{"key":"671_CR30","first-page":"201","volume-title":"Proceedings of the ACM SIGPLAN 1982 symposium on compiler construction","author":"GJ Chaitin","year":"1982","unstructured":"Chaitin GJ (1982) Register allocation and spilling via graph coloring. In: Proceedings of the ACM SIGPLAN 1982 symposium on compiler construction, pp 201\u2013207"},{"key":"671_CR31","volume-title":"Conference on programming language design and implementation","author":"P Briggs","year":"1992","unstructured":"Briggs P, Cooper KD, Torczon L (1992) Rematerialization. In: Conference on programming language design and implementation"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-011-0671-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-011-0671-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-011-0671-8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,14]],"date-time":"2019-06-14T15:02:55Z","timestamp":1560524575000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-011-0671-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8,30]]},"references-count":31,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2012,9]]}},"alternative-id":["671"],"URL":"https:\/\/doi.org\/10.1007\/s11227-011-0671-8","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8,30]]}}}