{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,6,23]],"date-time":"2023-06-23T04:35:03Z","timestamp":1687494903833},"reference-count":31,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2014,6,25]],"date-time":"2014-06-25T00:00:00Z","timestamp":1403654400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2014,10]]},"DOI":"10.1007\/s11227-014-1250-6","type":"journal-article","created":{"date-parts":[[2014,6,24]],"date-time":"2014-06-24T05:25:32Z","timestamp":1403587532000},"page":"385-407","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Probabilistic odd\u2013even: an adaptive wormhole routing algorithm for 2D mesh network-on-chip"],"prefix":"10.1007","volume":"70","author":[{"given":"Su","family":"Hu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wenzheng","family":"Xu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jing","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xiaola","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2014,6,25]]},"reference":[{"key":"1250_CR1","unstructured":"Oskin M, Torrellas J (2010) Laying a new foundation for IT: computer architecture for 2025 and beyond. In: Workshop on advancing computer architecture research (ACAR-II), September 20\u201321, 2010, Seattle"},{"key":"1250_CR2","doi-asserted-by":"crossref","unstructured":"O\u2019Kelly P (2013) Computer simulation of thermal plant operations. Costec Systems Pty Ltd., Brookvale (Sydney), p 32","DOI":"10.1007\/978-1-4614-4256-1"},{"key":"1250_CR3","unstructured":"Semiconductor Association (2006) The international technology roadmap for semiconductors (ITRS)"},{"key":"1250_CR4","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1132952.1132953","volume":"38","author":"T Bjerregaard","year":"2006","unstructured":"Bjerregaard T, Mahadevan S (2006) A survey of research and practices of network-on-chip. ACM Comput Surveys 38:1\u201351","journal-title":"ACM Comput Surveys"},{"key":"1250_CR5","doi-asserted-by":"crossref","unstructured":"Nikitin N, Chatterjee S, Cortadella J, Kishinevsky M, Ogras U (2010) Physical-aware link allocation and route assignment for chip multiprocessing. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1109\/NOCS.2010.22"},{"issue":"8","key":"1250_CR6","doi-asserted-by":"crossref","first-page":"3701","DOI":"10.1109\/TIE.2010.2081953","volume":"58","author":"T Mak","year":"2011","unstructured":"Mak T, Cheung PYK, Lam K, Luk W (2011) Adaptive routing in network-on-chips using a dynamic-programming network. IEEE Trans Ind Electr 58(8):3701\u20133716","journal-title":"IEEE Trans Ind Electr"},{"key":"1250_CR7","unstructured":"Duato J, Yalamanchili S, Ni L (2004) Interconnection networks an engineering approach. Morgan Kaufmann, San Francisco, pp 55\u201357"},{"key":"1250_CR8","doi-asserted-by":"crossref","first-page":"729","DOI":"10.1109\/71.877831","volume":"11","author":"GM Chiu","year":"2000","unstructured":"Chiu GM (2000) The odd-even turn model for adaptive routing. IEEE Trans Parallel Distrib Syst 11:729\u2013738","journal-title":"IEEE Trans Parallel Distrib Syst"},{"issue":"12","key":"1250_CR9","doi-asserted-by":"crossref","first-page":"1320","DOI":"10.1109\/71.250114","volume":"4","author":"J Duato","year":"1993","unstructured":"Duato J (1993) A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans Parallel Distrib Syst 4(12):1320\u20131331","journal-title":"IEEE Trans Parallel Distrib Syst"},{"key":"1250_CR10","doi-asserted-by":"crossref","unstructured":"Anjan KV, Pinkston TM (1995) An efficient fully adaptive deadlock recovery scheme: DISHA. In: Proceedings of the 22nd international symposium on computer architecture, pp 201\u2013210","DOI":"10.1109\/ISCA.1995.524561"},{"issue":"2","key":"1250_CR11","doi-asserted-by":"crossref","first-page":"62","DOI":"10.1109\/2.191995","volume":"26","author":"LM Ni","year":"1993","unstructured":"Ni LM, McKinley PK (1993) A survey of wormhole routing techniques in direct networks. Computer 26(2):62\u201376","journal-title":"Computer"},{"key":"1250_CR12","doi-asserted-by":"crossref","unstructured":"Glass CJ, Ni LM (1992) The turn model for adaptive routing. In: Proceedings of 19th annual international symposium on computer architecture, pp 278\u2013287","DOI":"10.1109\/ISCA.1992.753324"},{"key":"1250_CR13","doi-asserted-by":"crossref","unstructured":"Fu B, Han Y, Ma J, Li H, Li X (2011) An abacus turn model for time\/space-efficient reconfigutable routing. In: Proceedings of annual international symposium on computer architecture","DOI":"10.1145\/2000064.2000096"},{"key":"1250_CR14","doi-asserted-by":"crossref","unstructured":"Joshi A, Mutyam M (2011) Prevention flow-control for low latency torus networks-on-chip. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1145\/1999946.1999954"},{"key":"1250_CR15","doi-asserted-by":"crossref","unstructured":"Jin Y, Kim EJ, Yum KH (2010) Design and analysis of on-chip networks for large-scale cache systems. IEEE Trans Comput 59(3):332\u2013344","DOI":"10.1109\/TC.2009.130"},{"key":"1250_CR16","doi-asserted-by":"crossref","unstructured":"Zhao D, Wu R (2012) Overlaid mesh topology design and deadlock free routing in wireless network-on-chip. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1109\/NOCS.2012.11"},{"key":"1250_CR17","doi-asserted-by":"crossref","unstructured":"Kinsy MA, Cho MH, Shim KS, Lis M, Suh GE, Devadas S (2013) Optimal and heuristic application-aware oblivious routing. IEEE Trans Comput 62(1):59\u201373","DOI":"10.1109\/TC.2011.219"},{"issue":"3","key":"1250_CR18","doi-asserted-by":"crossref","first-page":"561","DOI":"10.1109\/TC.2011.226","volume":"62","author":"RS Ramanujam","year":"2013","unstructured":"Ramanujam RS, Lin B (2013) Randomized Throughput-optimal oblivious routing for torus networks. IEEE Trans Comput 62(3):561\u2013574","journal-title":"IEEE Trans Comput"},{"key":"1250_CR19","doi-asserted-by":"crossref","unstructured":"Ebrahimi M, Daneshtalab M, Farahnakian F, Plosila J, Liljeberg P, Palesi M, Tenhunen H (2012) HARAQ: congestion-aware learning model for highly adaptive routing algorithm in on-chip networks. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1109\/NOCS.2012.10"},{"key":"1250_CR20","doi-asserted-by":"crossref","unstructured":"Matsutani H, Take Y, Sasaki D, Kimura M, Ono Y, Nishiyama Y, Koibuchi M, Kuroda T, Amano H (2011) A vertical bubble flow network using inductive-coupling for 3-D CMPs. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1145\/1999946.1999955"},{"key":"1250_CR21","doi-asserted-by":"crossref","unstructured":"Hu J, Marculescu R (2004) DyAD: smart routing for networks-on-chip. In: ACM\/IEEE design automation conference (DAC)","DOI":"10.1145\/996566.996638"},{"key":"1250_CR22","doi-asserted-by":"crossref","unstructured":"Cong J, Liu CY, Reinman G (2010) ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip. In: ACM\/IEEE design automation conference (DAC)","DOI":"10.1145\/1837274.1837385"},{"issue":"4","key":"1250_CR23","doi-asserted-by":"crossref","first-page":"466","DOI":"10.1109\/71.219761","volume":"4","author":"WJ Dally","year":"1993","unstructured":"Dally WJ, Aoki H (1993) Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans Parallel Distrib Syst 4(4):466\u2013475","journal-title":"IEEE Trans Parallel Distrib Syst"},{"key":"1250_CR24","doi-asserted-by":"crossref","first-page":"809","DOI":"10.1109\/TC.2008.38","volume":"57","author":"G Ascia","year":"2008","unstructured":"Ascia G, Catania V, Palesi M (2008) Implementation and analysis of a new selection strategy for adaptive routing in networks-on-chip. IEEE Trans Comput 57:809\u2013820","journal-title":"IEEE Trans Comput"},{"key":"1250_CR25","doi-asserted-by":"crossref","unstructured":"Shin M, Kim J (2011) Leveraging torus topology with deadlock recovery for cost-efficient on-chip network. In: Proceedings IEEE 29th international conference on computer design (ICCD), pp 25\u201330","DOI":"10.1109\/ICCD.2011.6081371"},{"key":"1250_CR26","doi-asserted-by":"crossref","unstructured":"Lankes A, Wild T, Herkersdorf A, Sonntag S, Reinig H (2010) Comparison of deadlock recovery and avoidance mechanisms to approach message dependent deadlocks in on-chip networks. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1109\/NOCS.2010.11"},{"key":"1250_CR27","unstructured":"Tsai W, Chu K, Chen S, Hu Y (2010) TM-FAR: turn-model based fully adaptive routing for networks on chip. In: Proceedings of the 18th IEEE\/IFIP VLSI system on chip conference (VLSI-SoC), pp 19\u201324"},{"key":"1250_CR28","unstructured":"Hu S, Lin X (2012) A symmetric odd-even routing model in network-on-chip. In: Proceedings of the IEEE\/ACIS 11th international conference on computer and information science (ICIS), pp 457\u2013462"},{"key":"1250_CR29","unstructured":"Noxim (2008) Network-on-chip simulator. http:\/\/sourceforge.net\/projects\/noxim"},{"key":"1250_CR30","doi-asserted-by":"crossref","unstructured":"Dujaily RA, Mak T, Yakovlev A, Palesi M (2012) Embedded transitive closure network for run-time deadlock detection in networks-on-chip. IEEE Trans Parallel Distrib Syst 23(7):1205\u20131215","DOI":"10.1109\/TPDS.2011.275"},{"key":"1250_CR31","doi-asserted-by":"crossref","unstructured":"Kakoee MR, Bertacco V, Benini L (2011) A distributed and topology-agnostic approach for on-line NoC testing. In: ACM\/IEEE international symposium on networks-on-chip (NoCs)","DOI":"10.1145\/1999946.1999965"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-014-1250-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-014-1250-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-014-1250-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,8,11]],"date-time":"2019-08-11T21:15:12Z","timestamp":1565558112000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-014-1250-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,6,25]]},"references-count":31,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2014,10]]}},"alternative-id":["1250"],"URL":"https:\/\/doi.org\/10.1007\/s11227-014-1250-6","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2014,6,25]]}}}