{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T20:06:48Z","timestamp":1649189208280},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2015,4]]},"DOI":"10.1007\/s11227-014-1270-2","type":"journal-article","created":{"date-parts":[[2014,12,31]],"date-time":"2014-12-31T05:15:56Z","timestamp":1420002956000},"page":"1177-1195","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Dynamic-width reconfigurable parallel prefix circuits"],"prefix":"10.1007","volume":"71","author":[{"given":"Hatem M.","family":"El-Boghdadi","sequence":"first","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,1,1]]},"reference":[{"key":"1270_CR1","volume-title":"Parallel computation: models and methods","author":"SG Akl","year":"1997","unstructured":"Akl SG (1997) Parallel computation: models and methods. Prentice-Hall, Upper Saddle River"},{"key":"1270_CR2","volume-title":"Introduction to parallel algorithms and architectures: arrays, trees. Hypercubes","author":"FT Leighton","year":"1992","unstructured":"Leighton FT (1992) Introduction to parallel algorithms and architectures: arrays, trees. Hypercubes. Morgan Kaufmann, San Mateo"},{"issue":"3","key":"1270_CR3","doi-asserted-by":"crossref","first-page":"303","DOI":"10.1023\/B:SUPE.0000032783.66123.63","volume":"29","author":"A Datta","year":"2004","unstructured":"Datta A (2004) Multiple addition and prefix sum on a linear array with a reconfigurable pipelined bus system. J Supercomput 29(3):303\u2013317","journal-title":"J Supercomput"},{"issue":"1","key":"1270_CR4","doi-asserted-by":"crossref","first-page":"59","DOI":"10.1016\/0020-0190(95)00119-W","volume":"56","author":"T Hagerup","year":"1995","unstructured":"Hagerup T (1995) The parallel complexity of integer prefix summation. Inform Process Lett 56(1):59\u201364","journal-title":"Inform Process Lett"},{"issue":"2","key":"1270_CR5","doi-asserted-by":"crossref","first-page":"145","DOI":"10.1007\/BF01177744","volume":"32","author":"WJ Hsu","year":"1995","unstructured":"Hsu WJ, Page CV (1995) Parallel tree contraction and prefix computations on a large family of interconnection topologies. Acta Inform 32(2):145\u2013153","journal-title":"Acta Inform"},{"issue":"1","key":"1270_CR6","doi-asserted-by":"crossref","first-page":"97","DOI":"10.1016\/j.jpdc.2003.09.004","volume":"64","author":"Y-C Lin","year":"2004","unstructured":"Lin Y-C, Hsiao J-W (2004) A new approach to constructing optimal parallel prefix circuits with small depth. J Parallel Distrib Comput 64(1):97\u2013107","journal-title":"J Parallel Distrib Comput"},{"key":"1270_CR7","doi-asserted-by":"crossref","first-page":"1585","DOI":"10.1016\/j.jpdc.2005.05.017","volume":"65","author":"Y-C Lin","year":"2005","unstructured":"Lin Y-C, Su C-Y (2005) Faster optimal parallel prefix circuits: New algorithmic construction. J Parallel Distrib Comput 65:1585\u20131595","journal-title":"J Parallel Distrib Comput"},{"issue":"1","key":"1270_CR8","first-page":"41","volume":"16","author":"Y-C Lin","year":"2000","unstructured":"Lin Y-C, Lin CM (2000) Efficient parallel prefix algorithms on multicomputers. J Inform Sci Eng 16(1):41\u201364","journal-title":"J Inform Sci Eng"},{"key":"1270_CR9","unstructured":"Sheeran M, Parberry I (2006) A new approach to the design of optimal parallel prefix circuits. In: Technical report 2006, vol 1. Department of Computer Science and Engineering, Chalmers University of Technology, Goteborg"},{"issue":"2","key":"1270_CR10","doi-asserted-by":"crossref","first-page":"387","DOI":"10.1145\/1142155.1142162","volume":"11","author":"H Zhu","year":"2006","unstructured":"Zhu H, Cheng C-K, Graham R (2006) Constructing zero-deficiency parallel prefix circuits of minimum depth. ACM Trans Des Autom Electron Syst 11(2):387\u2013409","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"1270_CR11","unstructured":"Zhu H, Cheng C-K, Graham R (2009) Straightforward construction of depth-size optimal, parallel prefix circuits with fan-out 2. ACM Trans Des Autom Electron Syst 14(1):article 15"},{"issue":"8","key":"1270_CR12","first-page":"28","volume":"1","author":"Ashutosh Kumar","year":"2013","unstructured":"Kumar Ashutosh, Jain Rakesh (2013) Design of 64-bit parallel prefix VLSI adder for high speed arithmetic circuits. Int J Res Eng Sci (IJRES) 1(8):28\u201332","journal-title":"Int J Res Eng Sci (IJRES)"},{"issue":"2","key":"1270_CR13","doi-asserted-by":"crossref","first-page":"225","DOI":"10.1109\/TC.2005.26","volume":"54","author":"G Dimitrakopoulos","year":"2005","unstructured":"Dimitrakopoulos G, Nikolos D (2005) High-speed parallel-prefix VLSI Ling adders. IEEE Trans Comput 54(2):225\u2013231","journal-title":"IEEE Trans Comput"},{"key":"1270_CR14","doi-asserted-by":"crossref","unstructured":"Knowles S (2001) A family of adders. In: Proceedings of the 15th IEEE symposium on computer arithmetic, Vail, pp 277\u2013284","DOI":"10.1109\/ARITH.2001.930129"},{"key":"1270_CR15","doi-asserted-by":"crossref","unstructured":"Beaumont-Smith A, Lim C-C (2001) Parallel prefix adder design. In: Proceedings of the 15th IEEE symposium on computer arithmetic, Vail, pp 218\u2013225","DOI":"10.1109\/ARITH.2001.930122"},{"issue":"1","key":"1270_CR16","first-page":"33","volume":"7","author":"Y-C Lin","year":"1999","unstructured":"Lin Y-C (1999) Optimal parallel prefix circuits with fan-out 2 and corresponding parallel algorithms. Neural Parallel Sci Comput 7(1):33\u201342","journal-title":"Neural Parallel Sci Comput"},{"key":"1270_CR17","doi-asserted-by":"crossref","first-page":"382","DOI":"10.1016\/j.jpdc.2008.12.003","volume":"69","author":"Y-C Lin","year":"2009","unstructured":"Lin Y-C, Hung L-L (2009) Fast problem-size-independent parallel prefix circuits. J Parallel Distrib Comput 69:382\u2013388","journal-title":"J Parallel Distrib Comput"},{"key":"1270_CR18","doi-asserted-by":"crossref","unstructured":"Hatem M El-Boghdadi (2013), a class of almost-optimal size-independent parallel prefix circuits. J Parallel Distrib Comput 73:888\u2013894","DOI":"10.1016\/j.jpdc.2013.03.012"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-014-1270-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-014-1270-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-014-1270-2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T06:40:35Z","timestamp":1559371235000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-014-1270-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1,1]]},"references-count":18,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2015,4]]}},"alternative-id":["1270"],"URL":"https:\/\/doi.org\/10.1007\/s11227-014-1270-2","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,1,1]]}}}