{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T16:47:52Z","timestamp":1694537272728},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"9","license":[{"start":{"date-parts":[[2015,6,10]],"date-time":"2015-06-10T00:00:00Z","timestamp":1433894400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2015,9]]},"DOI":"10.1007\/s11227-015-1452-6","type":"journal-article","created":{"date-parts":[[2015,6,9]],"date-time":"2015-06-09T13:19:45Z","timestamp":1433855985000},"page":"3609-3636","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Synchronization algorithm for predictors for SDRAM memories"],"prefix":"10.1007","volume":"71","author":[{"given":"Vladimir V.","family":"Stankovic","sequence":"first","affiliation":[]},{"given":"Nebojsa Z.","family":"Milenkovic","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2015,6,10]]},"reference":[{"key":"1452_CR1","volume-title":"Memory systems: cache, DRAM, disk","author":"B Jacob","year":"2007","unstructured":"Jacob B, Ng S, Wang D (2007) Memory systems: cache, DRAM, disk. Morgan Kaufman, Massachusetts"},{"key":"1452_CR2","volume-title":"Computer architecture: a quantitative approach","author":"J Hennessy","year":"2011","unstructured":"Hennessy J, Patterson D (2011) Computer architecture: a quantitative approach, 5th edn. Morgan Kaufman, Massachusetts","edition":"5"},{"key":"1452_CR3","doi-asserted-by":"crossref","unstructured":"Hu Z, Kaxiras S, Martonosi M (2002) Timekeeping in the memory system: predicting and optimizing memory behavior. In: Proc. 29th annual international symposium on computer architecture (ISCA \u201902), pp 209\u2013220","DOI":"10.1145\/545214.545239"},{"issue":"4","key":"1452_CR4","doi-asserted-by":"crossref","first-page":"584","DOI":"10.1587\/transinf.E92.D.584","volume":"E92\u2013D","author":"V Stankovic","year":"2009","unstructured":"Stankovic V, Milenkovic N (2009) DRAM controller with a complete predictor. IEICE Trans Inf Syst E92\u2013D(4):584\u2013593","journal-title":"IEICE Trans Inf Syst"},{"key":"1452_CR5","doi-asserted-by":"crossref","unstructured":"Awasthi M, Nellans DW, Balasubramonian R, Davis A (2011) Prediction based DRAM row-buffer management in the Many-Core Era. In: Proc. international conf. parallel architectures and compilation, techniques, pp 183\u2013184","DOI":"10.1109\/PACT.2011.31"},{"key":"1452_CR6","doi-asserted-by":"crossref","unstructured":"Xu Y, Agarwal AS, Davis BT (2009) Prediction in dynamic SDRAM controller policies. In: Bertels K et al (eds) SAMOS 2009, LNCS 5657. Springer, Berlin, pp 128\u2013138","DOI":"10.1007\/978-3-642-03138-0_14"},{"key":"1452_CR7","unstructured":"Chiyuan M, Shuming C (2007) A DRAM precharge policy based on address analysis. In: Proc. 10th euromicro conf. digital system design architectures, methods and tools (DSD \u201907), pp 244\u2013248"},{"key":"1452_CR8","unstructured":"Park SI, Park IC (2003) History-based memory mode prediction for improving memory performance. In: Proc. international symp. circuits and systems (ISCAS \u201903), vol. 5, pp 185\u2013188"},{"key":"1452_CR9","unstructured":"Kahn O, Wilcox J (2004) Method for dynamically adjusting a memory page closing policy. United States Patent, Patent No. US 6,799,241 B2"},{"key":"1452_CR10","unstructured":"Fanning B (2003) Method for dynamically adjusting memory system paging policy. United States Patent, Patent No. US 6,604,186 B1"},{"key":"1452_CR11","unstructured":"Emerling BD (2004) Predictive optimizer for DRAM memory. United States Patent, Patent No. US 6,741,256 B2"},{"key":"1452_CR12","doi-asserted-by":"crossref","unstructured":"Chiyuan M, Xiaoqiang N (2014) A memory schedule policy oriented to stream architecture. In: Proc. international conf. on embedded and real-time computing systems and applications (RTCSA 14), pp 1\u20135","DOI":"10.1109\/RTCSA.2014.6910535"},{"key":"1452_CR13","doi-asserted-by":"crossref","unstructured":"Thomas G, Elhossini A, Juurlink B (2014) A generic implementation of a quantified predictor on FPGAs. In: Proc. 24th edition of the great lakes symposium on VLSI, pp 255\u2013260","DOI":"10.1145\/2591513.2591517"},{"key":"1452_CR14","doi-asserted-by":"crossref","unstructured":"Son YH, Seongil O, Ro Y, Lee JW, Ahn JH (2013) Reducing memory access latency with asymmetric DRAM bank organizations. In: Proc. 40th annual international symposium on computer architecture, pp 380\u2013391","DOI":"10.1145\/2485922.2485955"},{"key":"1452_CR15","unstructured":"Krimer E, Savransky G, Mondjak I, Doweck J (2013) Counter-based memory disambiguation techniques for selectively predicting load\/store conflicts. United States Patent, No. US 8,549,263 B2"},{"key":"1452_CR16","doi-asserted-by":"crossref","unstructured":"Yoon DH, Jeong MK, Sullivan M, Erez M (2012) The dynamic granularity memory system. In: Proc. 39th annual international symposium on computer architecture, pp 548\u2013559","DOI":"10.1109\/ISCA.2012.6237047"},{"key":"1452_CR17","doi-asserted-by":"crossref","unstructured":"El-Nacouzi M, Atta I, Papadopoulou M, Zebchuk J, Jerger NE, Moshovos A (2013) A dual grain hit-miss detector for large die-stacked DRAM caches. In: Proc. conf. on design, automation and test in Europe, pp 89\u201392","DOI":"10.7873\/DATE.2013.032"},{"key":"1452_CR18","unstructured":"Micron, DDR4 SDRAM UDIMM. Document name: atf16c1gx64az.pdf. www.micron.com"},{"key":"1452_CR19","doi-asserted-by":"crossref","unstructured":"Burger D, Austin TM (1997) The simplescalar tool set, Version 2.0, University of Wisconsin-Madison Computer Sciences Department Technical Report #1342","DOI":"10.1145\/268806.268810"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-015-1452-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-015-1452-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-015-1452-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T10:40:40Z","timestamp":1559385640000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-015-1452-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,6,10]]},"references-count":19,"journal-issue":{"issue":"9","published-print":{"date-parts":[[2015,9]]}},"alternative-id":["1452"],"URL":"https:\/\/doi.org\/10.1007\/s11227-015-1452-6","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2015,6,10]]}}}