{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T23:06:02Z","timestamp":1747868762507},"reference-count":41,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2016,10,28]],"date-time":"2016-10-28T00:00:00Z","timestamp":1477612800000},"content-version":"unspecified","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2017,5]]},"DOI":"10.1007\/s11227-016-1905-6","type":"journal-article","created":{"date-parts":[[2016,10,28]],"date-time":"2016-10-28T14:21:19Z","timestamp":1477664479000},"page":"2098-2129","update-policy":"http:\/\/dx.doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["A heuristic clustering approach to use case-aware application-specific network-on-chip synthesis"],"prefix":"10.1007","volume":"73","author":[{"given":"Fatemeh","family":"Vardi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ahmad","family":"Khadem-Zadeh","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Midia","family":"Reshadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2016,10,28]]},"reference":[{"key":"1905_CR1","first-page":"29","volume":"6","author":"M Agarwal","year":"2013","unstructured":"Agarwal M, Dubey R, Jain N, Raghuvanshi D (2013) Comparative analysis of different topologies based on network-on-chip architectures. Int J Electron Commun Eng 6:29\u201340","journal-title":"Int J Electron Commun Eng"},{"key":"1905_CR2","doi-asserted-by":"publisher","first-page":"2806","DOI":"10.1109\/TPDS.2014.2358218","volume":"26","author":"V Sehgal","year":"2014","unstructured":"Sehgal V (2014) Markovian models based stochastic communication in networks-in-package. IEEE Trans Parallel Distrib Syst 26:2806\u20132821","journal-title":"IEEE Trans Parallel Distrib Syst"},{"key":"1905_CR3","doi-asserted-by":"publisher","unstructured":"Henkel J, Wolf W, Chakradhar S (2004) On-chip networks: a scalable, communication-centric embedded system design paradigm. In: 17th International Conference on VLSI Design, pp 845\u2013851","DOI":"10.1109\/ICVD.2004.1261037"},{"key":"1905_CR4","first-page":"1","volume":"12","author":"HG Lee","year":"2008","unstructured":"Lee HG, Chang N, Ogras UY, Marculescu R (2008) On-chip communication architecture exploration: a quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACM Trans Des Autom Electron Syst 12:1\u201320","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"1905_CR5","first-page":"516","volume":"2","author":"N Choudhary","year":"2013","unstructured":"Choudhary N (2013) Migration of on-chip networks from 2 dimensional plane to 3 dimensional plane. Int J Eng Adv Technol 2:516\u2013519","journal-title":"Int J Eng Adv Technol"},{"key":"1905_CR6","doi-asserted-by":"publisher","first-page":"102","DOI":"10.1016\/j.vlsi.2015.07.017","volume":"52","author":"A Cilardo","year":"2016","unstructured":"Cilardo A, Fusella E (2016) Design automation for application-specific on-chip interconnects: a survey. INTEGRATION VLSI J 52:102\u2013121","journal-title":"INTEGRATION VLSI J"},{"key":"1905_CR7","doi-asserted-by":"publisher","unstructured":"Thapliyal H, Arabnia Hamid R, Srinivas MB (2009) Efficient reversible logic design of BCD subtractors. Trans Comput Sci J 3, 99\u2013121. Springer, Berlin","DOI":"10.1007\/978-3-642-00212-0_6"},{"key":"1905_CR8","unstructured":"Balasubramanian P, Arisaka R, Arabnia Hamid R (2012) RB_DSOP: a rule based disjoint sum of products synthesis method. In: Proceedings of the 2012 International Conference on Computer Design, pp 39\u201343"},{"key":"1905_CR9","unstructured":"Balasubramanian P, Edwards DA, Arabnia Hamid R (2011) Robust asynchronous carry lookahead adders. In: Proceedings of the International Conference on Computer Design, pp 119\u2013124"},{"key":"1905_CR10","doi-asserted-by":"publisher","unstructured":"Thapliyal H, Jayashree HV, Nagamani AN, Arabnia Hamid R (2013) Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. In: Transactions in computational science. Springer, Berlin, pp 73\u201397","DOI":"10.1007\/978-3-642-35840-1_4"},{"key":"1905_CR11","unstructured":"Gopineedi PD, Thapliyal H, Srinivas MB, Arabnia Hamid R (2006) Novel and efficient 4:2 and 5:2 compressors with minimum number of transistors designed for low-power operations. In: Proceedings of the 2006 International Conference on Embedded Systems and Applications, pp 160\u2013166"},{"key":"1905_CR12","doi-asserted-by":"publisher","unstructured":"Todorov V, Mueller-Gritschneder D, Reinig H, Schlichtmann U (2013) A spectral clustering approach to application-specific network-on-chip synthesis. In: International Conference on Automation and Test Design, pp 1783\u20131788","DOI":"10.7873\/DATE.2013.358"},{"key":"1905_CR13","doi-asserted-by":"publisher","unstructured":"Verma A, Multani PS, Mueller-Gritschneder D, Todorov V (2013) A greedy approach for latency-bounded deadlock-free routing path allocation for application-specific NoCs. In: Seventh IEEE\/ACM International Symposium on Networks on Chip, pp 1\u20137","DOI":"10.1109\/NoCS.2013.6558417"},{"key":"1905_CR14","doi-asserted-by":"publisher","first-page":"1503","DOI":"10.1109\/TCAD.2014.2331556","volume":"33","author":"V Todorov","year":"2014","unstructured":"Todorov V, Mueller-Gritschneder D, Reinig H, Schlichtmann U (2014) Deterministic synthesis of hybrid application-specific network-on-chip topologies. IEEE Trans Comput Aided Des Integr Circ Syst 33:1503\u20131516","journal-title":"IEEE Trans Comput Aided Des Integr Circ Syst"},{"key":"1905_CR15","unstructured":"Chen J, Li C, Gillard P (2011) Network-on-chip (NoC) topologies and performance. Proceedings of the 2011 Newfoundland Electrical and Computer Engineering Conference, pp 1\u20136"},{"key":"1905_CR16","unstructured":"Ziegelmann M (2010) Constrained shortest paths and related problems: constrained network optimization. VDM Verlag, Germany"},{"key":"1905_CR17","unstructured":"Thapliyal H, Srinivas MB, Arabnia Hamid R (2005) A need of quantum computing: reversible logic synthesis of parallel binary adder-subtractor. In: Proceedings of the 2005 International Conference on Embedded Systems and Applications, pp 60\u201368"},{"key":"1905_CR18","doi-asserted-by":"publisher","unstructured":"Thapliyal H, Arabnia Hamid R, Vinod AP (2006) Combined integer and floating point multiplication architecture (CIFM) for FPGAs and its reversible logic implementation. In: 49th IEEE international Midwest Symposium on Circuits and Systems, pp 148\u2013154","DOI":"10.1109\/MWSCAS.2006.382306"},{"key":"1905_CR19","unstructured":"Thapliyal H, Arabnia Hamid R (2006) Reversible programmable logic array (RPLA) using Fredkin and Feynman gates for industrial electronics and applications. In: Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, pp 70\u201374"},{"key":"1905_CR20","unstructured":"Thapliyal H, Arabnia Hamid R, Bajpai R, Sharma KK (2007) Combined integer and variable precision (CIVP) floating point multiplication architecture for FPGAs. In: Proceedings of 2007 International Conference on Parallel & Distributed Processing Techniques & Applications, pp 449\u2013450"},{"key":"1905_CR21","doi-asserted-by":"publisher","first-page":"4260","DOI":"10.1007\/s11227-015-1521-x","volume":"71","author":"S Johari","year":"2015","unstructured":"Johari S, Sehgal VK (2015) Master-based routing algorithm and communication-based cluster topology for 2D NoC. J Supercomput 71:4260\u20134286","journal-title":"J Supercomput"},{"key":"1905_CR22","doi-asserted-by":"crossref","unstructured":"Tahdhighi M, Mousavi M, Khadivi P, Bazargan K (2012) A new hybrid topology for network on chip. In: Proceedings of the 20th Iranian Conference of Electrical Engineering","DOI":"10.1109\/IranianCEE.2012.6292457"},{"key":"1905_CR23","doi-asserted-by":"publisher","unstructured":"Zhao H et al (2012) A hybrid NoC design for cache coherence optimization for chip multiprocessors. In: Proceedings of the 49th Annual Design Automation Conference, pp 834\u2013842","DOI":"10.1145\/2228360.2228511"},{"key":"1905_CR24","doi-asserted-by":"publisher","first-page":"361","DOI":"10.1016\/j.sysarc.2013.05.013","volume":"56","author":"J Soumya","year":"2013","unstructured":"Soumya J, Santanu C (2013) Application-specific network-on-chip synthesis with flexible router placement. J Syst Architect 56:361\u2013371","journal-title":"J Syst Architect"},{"key":"1905_CR25","doi-asserted-by":"publisher","unstructured":"Zhong W, Yu B, Chen S, Yoshimura T (2011) Application-specific network-on-chip synthesis: cluster generation and network component insertion. In: 12th international symposium on quality electronic design, pp 1\u20138","DOI":"10.1109\/ISQED.2011.5770718"},{"key":"1905_CR26","doi-asserted-by":"publisher","unstructured":"Khan GN, Tino A (2012) Synthesis of NoC interconnects for custom MPSoC architectures. In: Sixth IEEE\/ACM International Symposium on networks on Chip, pp 75\u201382","DOI":"10.1109\/NOCS.2012.16"},{"key":"1905_CR27","doi-asserted-by":"publisher","unstructured":"Huang B, Chen S, Zhong W, Yoshimura T (2013) Topology-aware floorplanning for 3D application-specific network-on-chip synthesis. In: IEEE International Symposium on Circuits and Systems, pp 1732\u20131735","DOI":"10.1109\/ISCAS.2013.6572199"},{"key":"1905_CR28","first-page":"22","volume":"85","author":"S Jain","year":"2014","unstructured":"Jain S, Choudhary N, Singh D (2014) STG-NoC: a tool for generating energy optimized custom built NoC topology. Int J Comput Appl 85:22\u201326","journal-title":"Int J Comput Appl"},{"key":"1905_CR29","doi-asserted-by":"publisher","first-page":"239","DOI":"10.1049\/iet-cdt:20070049","volume":"2","author":"KC Chang","year":"2008","unstructured":"Chang KC, Chen TF (2008) Low-power algorithm for automatic topology generation for application-specific networks on chips. IET Comput Digital Tech 2:239\u2013249","journal-title":"IET Comput Digital Tech"},{"key":"1905_CR30","first-page":"436","volume":"292","author":"M Maheswari","year":"2012","unstructured":"Maheswari M, Seetharaman G (2012) Implementation of application specific network-on-chip architectures on reconfigurable device using topology generation algorithm with genetic algorithm based optimization technique. Chap Commun Comput Inf Sci 292:436\u2013445","journal-title":"Chap Commun Comput Inf Sci"},{"key":"1905_CR31","doi-asserted-by":"publisher","first-page":"318","DOI":"10.1049\/iet-cdt.2011.0080","volume":"6","author":"S Tosun","year":"2012","unstructured":"Tosun S, Ar Y, Ozdemir S (2012) Application-specific topology generation algorithms for network-on-chip design. Comput Digit Techn IET 6:318\u2013333","journal-title":"Comput Digit Techn IET"},{"key":"1905_CR32","doi-asserted-by":"publisher","unstructured":"Ababei C (2010) Efficient congestion-oriented custom network-on-chip topology synthesis. In: International Conference on Reconfigurable Computing and FPGAs, pp 352\u2013357","DOI":"10.1109\/ReConFig.2010.27"},{"key":"1905_CR33","unstructured":"Leary G, Chatha K (2012) A holistic approach to network-on-chip synthesis. In: International Conference on Hardware\/Software Codesign and System Synthesis, pp 213\u2013222"},{"key":"1905_CR34","first-page":"1","volume":"11","author":"CL Li","year":"2014","unstructured":"Li CL, Lee JH, Yang JS, Han TH (2014) Communication-aware custom topology generation for VFI network-on-chip. IEICE Electron Express 11:1\u20138","journal-title":"IEICE Electron Express"},{"key":"1905_CR35","doi-asserted-by":"publisher","first-page":"343","DOI":"10.1016\/j.micpro.2009.03.002","volume":"33","author":"H Elmiligi","year":"2009","unstructured":"Elmiligi H, Morgan AA, Watheq El-Kharashi M, Gebali F (2009) Power optimization for application-specific networks-on-chips: A topology-based approach. Microprocess Microsyst 33:343\u2013355","journal-title":"Microprocess Microsyst"},{"key":"1905_CR36","unstructured":"Yu B, Dong S, Chen S, Goto S (2010) Floorplanning and topology generation for application-specific network-on-chip. In: 15th Asia and South Pacific Design Automation Conference (ASP-DAC)"},{"key":"1905_CR37","unstructured":"Intel Mobile Communications GmbH (2013) Smartphone example (online). http:\/\/www.eda.ei.tum.de\/uploads\/media\/SoCExample1.xml"},{"key":"1905_CR38","doi-asserted-by":"publisher","unstructured":"Chen-Ling C, Marculescu R (2008) Contention-aware application mapping for network-on-chip communication architectures. In: IEEE International Conference on Computer Design, pp 164\u2013169","DOI":"10.1109\/ICCD.2008.4751856"},{"key":"1905_CR39","first-page":"304","volume":"896","author":"S Murali","year":"2004","unstructured":"Murali S, De Micheli G (2004) Bandwidth-constrained mapping of cores onto NoC architectures. Conf Des Autom Test 2 896:304","journal-title":"Conf Des Autom Test 2"},{"key":"1905_CR40","doi-asserted-by":"publisher","unstructured":"Kahng AB, Lin B, Nath S (2012) Explicit modeling of control and data for improved NoC router estimation. In: Design Automation Conference (DAC), pp 392\u2013397","DOI":"10.1145\/2228360.2228430"},{"key":"1905_CR41","unstructured":"Orion software release (online). http:\/\/vlsicad.ucsd.edu\/ORION3\/index.html"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-016-1905-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-016-1905-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-016-1905-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,9,15]],"date-time":"2019-09-15T04:06:28Z","timestamp":1568520388000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-016-1905-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,10,28]]},"references-count":41,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017,5]]}},"alternative-id":["1905"],"URL":"https:\/\/doi.org\/10.1007\/s11227-016-1905-6","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,10,28]]}}}