{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,6,26]],"date-time":"2025-06-26T04:09:55Z","timestamp":1750910995580,"version":"3.41.0"},"reference-count":49,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2017,9,20]],"date-time":"2017-09-20T00:00:00Z","timestamp":1505865600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2017,9,20]],"date-time":"2017-09-20T00:00:00Z","timestamp":1505865600000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/100008902","name":"Los Alamos National Laboratory","doi-asserted-by":"publisher","award":["LA-UR-17-24198"],"award-info":[{"award-number":["LA-UR-17-24198"]}],"id":[{"id":"10.13039\/100008902","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1007\/s11227-017-2144-1","type":"journal-article","created":{"date-parts":[[2017,9,20]],"date-time":"2017-09-20T07:29:03Z","timestamp":1505892543000},"page":"665-695","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["A performance study of the time-varying cache behavior: a study on APEX, Mantevo, NAS, and PARSEC"],"prefix":"10.1007","volume":"74","author":[{"given":"Nafiul A.","family":"Siddique","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Patricia A.","family":"Grubel","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdel-Hameed A.","family":"Badawy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jeanine","family":"Cook","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,9,20]]},"reference":[{"issue":"4","key":"2144_CR1","doi-asserted-by":"publisher","first-page":"37","DOI":"10.1145\/1964218.1964225","volume":"38","author":"AF Rodrigues","year":"2011","unstructured":"Rodrigues AF, Hemmert KS, Barrett BW, Kersey C, Oldfield R, Weston M, Risen R, Cook J, Rosenfeld P, CooperBalls E, Jacob B (2011) The structural simulation toolkit. SIGMETRICS Perform Eval Rev 38(4):37\u201342","journal-title":"SIGMETRICS Perform Eval Rev"},{"issue":"1","key":"2144_CR2","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf WA, McKee SA (1995) Hitting the memory wall: implications of the obvious. ACM SIGARCH Comput Archit News 23(1):20\u201324","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"2144_CR3","volume-title":"Computer architecture: a quantitative approach","author":"JL Hennessy","year":"2011","unstructured":"Hennessy JL, Patterson DA (2011) Computer architecture: a quantitative approach, 5th edn. Morgan Kaufmann Publishers Inc., San Francisco","edition":"5"},{"key":"2144_CR4","doi-asserted-by":"crossref","unstructured":"Siddique NA, Grubel P, Badawy AHA and Cook J (2016) Cache utilization as a locality metric\u2014a case study on the mantevo suite. In: 2016 International Conference on Computational Science and Computational Intelligence (CSCI), pp 549\u2013554","DOI":"10.1109\/CSCI.2016.0110"},{"key":"2144_CR5","doi-asserted-by":"crossref","unstructured":"Ramaswamy S and Yalamanchili S (2008) An utilization driven framework for energy efficient caches. In: Proceedings of the 15th International Conference on High Performance Computing, ser. HiPC\u201908, Springer, Berlin, Heidelberg, pp 583\u2013594","DOI":"10.1007\/978-3-540-89894-8_50"},{"key":"2144_CR6","doi-asserted-by":"crossref","unstructured":"Kumar S, Zhao H, Shriraman A, Matthews E, Dwarkadas S and Shannon L (2012) Amoeba-cache: adaptive blocks for eliminating waste in the memory hierarchy. In: MICRO, IEEE Computer Society, pp 376\u2013388","DOI":"10.1109\/MICRO.2012.42"},{"key":"2144_CR7","doi-asserted-by":"crossref","unstructured":"Kumar S and Wilkerson C (1998) Exploiting spatial locality in data caches using spatial footprints. In: Proceedings of the 25th Annual International Symposium on Computer Architecture, ser. ISCA \u201998, IEEE Computer Society, Washington, pp 357\u2013368","DOI":"10.1109\/ISCA.1998.694794"},{"key":"2144_CR8","volume-title":"Improving cache utilisation","author":"JR Srinivasan","year":"2011","unstructured":"Srinivasan JR (2011) Improving cache utilisation. University of Cambridge, Cambridge"},{"key":"2144_CR9","unstructured":"Todi R (2001) Speclite: using representative samples to reduce spec cpu2000 workload. In: Proceedings of the Fourth Annual IEEE International Workshop on Workload Characterization. WWC-4 (Cat. No.01EX538)"},{"key":"2144_CR10","doi-asserted-by":"crossref","unstructured":"Sherwood T, Perelman E, Calder B (2001) Basic block distribution analysis to find periodic behavior and simulation points in applications. In: Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques, pp 3\u201314","DOI":"10.1109\/PACT.2001.953283"},{"key":"2144_CR11","doi-asserted-by":"crossref","unstructured":"Patil H, Cohn R, Charney M, Kapoor R, Sun A and Karunanidhi A (2004) Pinpointing representative portions of large intel$$\\textregistered $$itanium$$\\textregistered $$programs with dynamic instrumentation. In: Proceedings of the 37th Annual IEEE\/ACM International Symposium on Microarchitecture, ser. MICRO 37, IEEE Computer Society, Washington, pp 81\u201392. [Online]. http:\/\/dx.doi.org\/10.1109\/MICRO.2004.28","DOI":"10.1109\/MICRO.2004.28"},{"key":"2144_CR12","unstructured":"Luk C-K, Cohn R, Muth R, Patil H, Klauser A, Lowney G, Wallace S, Reddi VJ and Hazelwood K (2005) Pin: building customized program analysis tools with dynamic instrumentation. In: Proceedings of the 2005 ACM SIGPLAN Conference on Programming Language Design and Implementation, ser. PLDI \u201905, ACM, New York, pp 190\u2013200"},{"key":"2144_CR13","doi-asserted-by":"crossref","unstructured":"Qayum M, Badawy A-H and Cook J (2017) Dadhtm: Low overhead dynamically adaptive hardware transactional memory for large graphs\u2014a scalability study. In: Proceedings of 17th IEEE International Conference on Scalable Computing and Communications (ScalCom). IEEE","DOI":"10.1109\/UIC-ATC.2017.8397653"},{"key":"2144_CR14","doi-asserted-by":"crossref","unstructured":"Weinberg J, McCracken MO, Strohmaier E and Snavely A (2005) Quantifying locality in the memory access patterns of hpc applications. In: Proceedings of the 2005 ACM\/IEEE Conference on Supercomputing, ser. SC \u201905, IEEE Computer Society, Washington, p 50. [Online]. https:\/\/doi.org\/10.1109\/SC.2005.59","DOI":"10.1109\/SC.2005.59"},{"key":"2144_CR15","doi-asserted-by":"crossref","unstructured":"Strohmaier E and Shan H (2004) Architecture independent performance characterization and benchmarking for scientific applications. In: The IEEE Computer Society\u2019s 12th Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, 2004. (MASCOTS 2004). Proceedings, pp 467\u2013474. [Online]. http:\/\/www.nersc.gov\/research-and-development\/apex\/apex-benchmarks\/","DOI":"10.1109\/MASCOT.2004.1348302"},{"key":"2144_CR16","unstructured":"Heroux MA, Doerfler DW, Crozier PS, Willenbring JM, Edwards HC, Williams A, Rajan M, Keiter ER, Thornquist HK and Numrich RW (2009) Improving Performance via Mini-applications, Sandia National Laboratories, Technical Report SAND2009-5574, [Online]. https:\/\/mantevo.org\/packages\/"},{"key":"2144_CR17","unstructured":"Bailey DH, Barszcz E, Barton JT, Browning DS, Carter RL, Dagum L, Fatoohi RA, Frederickson PO, Lasinski TA, Schreiber RS, Simon HD, Venkatakrishnan V and Weeratunga SK (1991) The nas parallel benchmarks&mdash;summary and preliminary results. In: Proceedings of the 1991 ACM\/IEEE Conference on Supercomputing, ser. Supercomputing \u201991, ACM, New York, pp 158\u2013165. [Online]. http:\/\/doi.acm.org\/10.1145\/125826.125925"},{"key":"2144_CR18","doi-asserted-by":"crossref","unstructured":"Bienia C, Kumar S, Singh JP and Li K (2008) The parsec benchmark suite: characterization and architectural implications. In: Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, ser. PACT \u201908, ACM, New York, pp 72\u201381. [Online]. http:\/\/doi.acm.org\/10.1145\/1454115.1454128","DOI":"10.1145\/1454115.1454128"},{"key":"2144_CR19","doi-asserted-by":"crossref","unstructured":"Banakar R, Steinke S, Lee B-S, Balakrishnan M and Marwedel P (2002) Scratchpad memory: design alternative for cache on-chip memory in embedded systems. In: Proceedings of the Tenth International Symposium on Hardware\/Software Codesign, ser. CODES \u201902, ACM, New York, pp 73\u201378","DOI":"10.1145\/774789.774805"},{"key":"2144_CR20","doi-asserted-by":"crossref","unstructured":"Hoste K and Eeckhout L (2006) Comparing benchmarks using key microarchitecture-independent characteristics. In: 2006 IEEE International Symposium on Workload Characterization, pp 83\u201392","DOI":"10.1109\/IISWC.2006.302732"},{"issue":"6","key":"2144_CR21","doi-asserted-by":"publisher","first-page":"769","DOI":"10.1109\/TC.2006.85","volume":"55","author":"A Joshi","year":"2006","unstructured":"Joshi A, Phansalkar A, Eeckhout L, John LK (2006) Measuring benchmark similarity using inherent program characteristics. IEEE Trans Comput 55(6):769\u2013782. doi: 10.1109\/TC.2006.85","journal-title":"IEEE Trans Comput"},{"issue":"5","key":"2144_CR22","doi-asserted-by":"publisher","first-page":"45","DOI":"10.1145\/635508.605403","volume":"36","author":"T Sherwood","year":"2002","unstructured":"Sherwood T, Perelman E, Hamerly G, Calder B (2002) Automatically characterizing large scale program behavior. SIGOPS Op Syst Rev 36(5):45\u201357. doi: 10.1145\/635508.605403","journal-title":"SIGOPS Op Syst Rev"},{"key":"2144_CR23","doi-asserted-by":"crossref","unstructured":"Panda R and John LK (2014) Data analytics workloads: characterization and similarity analysis. In: 2014 IEEE 33rd International Performance Computing and Communications Conference (IPCCC), pp 1\u20139","DOI":"10.1109\/PCCC.2014.7017065"},{"key":"2144_CR24","doi-asserted-by":"crossref","unstructured":"Seo S, Jo G, Lee J (2011) Performance characterization of the nas parallel benchmarks in opencl. In: 2011 IEEE International Symposium on Workload Characterization (IISWC), pp 137\u2013148","DOI":"10.1109\/IISWC.2011.6114174"},{"key":"2144_CR25","doi-asserted-by":"crossref","unstructured":"Coplin J and Burtscher M (2016) Energy, power, and performance characterization of gpgpu benchmark programs. In: 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), pp 1190\u20131199","DOI":"10.1109\/IPDPSW.2016.164"},{"key":"2144_CR26","unstructured":"Peachey J, Bunt R and Colbourn C (1983) Towards an intrinsic measure of program locality. In: Berg H, Howden W, Panko R, Sprague R, Shriver B, Walker T, Cousins T (eds) Proceedings of the Hawaii International Conference on System Science, pp 128\u2013137"},{"key":"2144_CR27","unstructured":"Beyls K and DHollander EH (2001) Reuse distance as a metric for cache behavior. In: Proceedings of The Iasted Conference on Parallel and Distributed Computing and Systems, pp 617\u2013662"},{"key":"2144_CR28","doi-asserted-by":"publisher","unstructured":"Ding C, Zhong Y (2003) Predicting whole-program locality through reuse distance analysis. SIGPLAN Notices 38(5):245\u2013257. doi: 10.1145\/780822.781159","DOI":"10.1145\/780822.781159"},{"key":"2144_CR29","doi-asserted-by":"crossref","unstructured":"Johnson TL, Merten MC and Hwu W-MW (1997) Run-time spatial locality detection and optimization. In: Proceedings of the 30th Annual ACM\/IEEE International Symposium on Microarchitecture, ser. MICRO 30, IEEE Computer Society, Washington, pp 57\u201364. [Online]. http:\/\/dl.acm.org\/citation.cfm?id=266800.266806","DOI":"10.1109\/MICRO.1997.645797"},{"issue":"6","key":"2144_CR30","doi-asserted-by":"publisher","first-page":"651","DOI":"10.1109\/12.286299","volume":"43","author":"J Torrellas","year":"1994","unstructured":"Torrellas J, Lam HS, Hennessy JL (1994) False sharing and spatial locality in multiprocessor caches. IEEE Trans Comput 43(6):651\u2013663","journal-title":"IEEE Trans Comput"},{"issue":"5","key":"2144_CR31","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1145\/301631.301668","volume":"34","author":"Y Song","year":"1999","unstructured":"Song Y, Li Z (1999) New tiling techniques to improve cache temporal locality. SIGPLAN Notices 34(5):215\u2013228. doi: 10.1145\/301631.301668","journal-title":"SIGPLAN Notices"},{"issue":"2","key":"2144_CR32","doi-asserted-by":"publisher","first-page":"78","DOI":"10.1147\/sj.92.0078","volume":"9","author":"RL Mattson","year":"1970","unstructured":"Mattson RL, Gecsei J, Slutz DR, Traiger IL (1970) Evaluation techniques for storage hierarchies. IBM Syst J 9(2):78\u2013117","journal-title":"IBM Syst J"},{"key":"2144_CR33","doi-asserted-by":"crossref","unstructured":"Alkohlani W and Cook J (2012) Towards performance predictive application-dependent workload characterization. In: High Performance Computing, Networking, Storage and Analysis (SCC), 2012 SC Companion, pp 426\u2013436","DOI":"10.1109\/SC.Companion.2012.62"},{"key":"2144_CR34","unstructured":"Bird S, Phansalkar A, John LK, Mercas A and Idukuru R (2007) Performance characterization of SPEC CPU benchmarks on Intel\u2019s Core microarchitecture based processor. In: SPEC Benchmark Workshop"},{"issue":"1","key":"2144_CR35","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1109\/2.67193","volume":"24","author":"TM Conte","year":"1991","unstructured":"Conte TM, Hwu W-MW (1991) Benchmark characterization. Computer 24(1):48\u201356","journal-title":"Computer"},{"key":"2144_CR36","doi-asserted-by":"crossref","unstructured":"Li S, Qiao L, Tang Z, Cheng B and Gao X (2009) Performance characterization of spec cpu2006 benchmarks on intel and amd platform. In: Education Technology and Computer Science, 2009. ETCS \u201909. First International Workshop on, vol\u00a02, pp 116\u2013121","DOI":"10.1109\/ETCS.2009.288"},{"issue":"5","key":"2144_CR37","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/MM.2009.74","volume":"29","author":"J Poovey","year":"2009","unstructured":"Poovey J, Conte T, Levy M, Gal-On S (2009) A benchmark characterization of the eembc benchmark suite. Micro IEEE 29(5):18\u201329","journal-title":"Micro IEEE"},{"issue":"2","key":"2144_CR38","doi-asserted-by":"publisher","first-page":"412","DOI":"10.1145\/1273440.1250713","volume":"35","author":"A Phansalkar","year":"2007","unstructured":"Phansalkar A, Joshi A, John LK (2007) Analysis of redundancy and application balance in the spec cpu2006 benchmark suite. SIGARCH Comput Archit News 35(2):412\u2013423","journal-title":"SIGARCH Comput Archit News"},{"issue":"1","key":"2144_CR39","doi-asserted-by":"publisher","first-page":"69","DOI":"10.1145\/1241601.1241616","volume":"35","author":"A Phansalkar","year":"2007","unstructured":"Phansalkar A, Joshi A, John L (2007) Subsetting the spec cpu2006 benchmark suite. SIGARCH Comput Archit News 35(1):69\u201376","journal-title":"SIGARCH Comput Archit News"},{"issue":"2","key":"2144_CR40","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/MM.2010.31","volume":"30","author":"P Conway","year":"2010","unstructured":"Conway P, Kalyanasundharam N, Donley G, Lepak K, Hughes B (2010) Cache hierarchy and memory subsystem of the amd opteron processor. Micro IEEE 30(2):16\u201329","journal-title":"Micro IEEE"},{"key":"2144_CR41","doi-asserted-by":"crossref","unstructured":"Ye D, Ray J, Harle C and Kaeli D (2006) Performance characterization of spec cpu2006 integer benchmarks on x86-64 architecture. In: 2006 IEEE International Symposium on Workload Characterization, pp 120\u2013127","DOI":"10.1109\/IISWC.2006.302736"},{"key":"2144_CR42","doi-asserted-by":"crossref","unstructured":"Siddique NA, Grubel PA and Badawy A-H (2017) The time-varying nature of cache utilization a case study on the mantevo and apex benchmarks. In: To Appear in Proceedings of the 14th IEEE Conference on Advanced and Trusted Computing (ATC 2017), San Francisco","DOI":"10.1109\/UIC-ATC.2017.8397629"},{"key":"2144_CR43","series-title":"Lecture notes in computer science","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1007\/978-3-319-17248-4_6","volume-title":"High performance computing systems. performance modeling, benchmarking, and simulation","author":"W Alkohlani","year":"2015","unstructured":"Alkohlani W, Cook J, Siddique N (2015) Insight into application performance using application-dependent characteristics. In: Jarvis SA, Wright SA, Hammond SD (eds) High performance computing systems. performance modeling, benchmarking, and simulation. Lecture notes in computer science. Springer, Berlin, pp 107\u2013128"},{"key":"2144_CR44","doi-asserted-by":"crossref","unstructured":"Perarnau S, Tchiboukdjian M and Huard G (2011) Controlling cache utilization of hpc applications. In: Proceedings of the International Conference on Supercomputing, ser. ICS \u201911, ACM, New York, pp 295\u2013304. [Online]. http:\/\/doi.acm.org\/10.1145\/1995896.1995942","DOI":"10.1145\/1995896.1995942"},{"key":"2144_CR45","doi-asserted-by":"crossref","unstructured":"Deshpande AM and Draper JT (2016) A new metric to measure cache utilization for hpc workloads. In: Proceedings of the Second International Symposium on Memory Systems, ser. MEMSYS \u201916, ACM, New York, pp 10\u201317. [Online]. http:\/\/doi.acm.org\/10.1145\/2989081.2989125","DOI":"10.1145\/2989081.2989125"},{"key":"2144_CR46","doi-asserted-by":"crossref","unstructured":"Nai L, Xia Y, Tanase IG, Kim H and Lin C-Y (2015) Graphbig: understanding graph computing in the context of industrial solutions. In: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis, ser. SC \u201915, ACM, New York, pp 69:1\u201369:12. [Online]. http:\/\/doi.acm.org\/10.1145\/2807591.2807626","DOI":"10.1145\/2807591.2807626"},{"key":"2144_CR47","doi-asserted-by":"crossref","unstructured":"Siddique NA, Badawy AHA, Cook J and Resnick D (2016) Lmstr: local memory store the case for hardware controlled scratchpad memory for general purpose processors. In: 2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC), pp 1\u20138","DOI":"10.1109\/PCCC.2016.7820661"},{"key":"2144_CR48","doi-asserted-by":"crossref","unstructured":"Siddique NA, Badawy A-HA, Cook J and Resnick D (2017) Local memory store (lmstr): a hardware controlled shared scratchpad for multicores. In: To Appear in Proceedings of the 14th IEEE Conference on Advanced and Trusted Computing (ATC 2017), San Francisco","DOI":"10.1109\/UIC-ATC.2017.8397630"},{"key":"2144_CR49","doi-asserted-by":"crossref","unstructured":"Siddique NA, Badawy AHA, Cook J and Resnick D (2017) Lmstr: exploring shared hardware controlled scratchpad memory for multicores. In: To Appear in Proceedings of the International Symposium on Memory Systems 2017 (MEMSYS17), Virginia","DOI":"10.1145\/3132402.3132440"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-017-2144-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-017-2144-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-017-2144-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,6,25]],"date-time":"2025-06-25T20:34:48Z","timestamp":1750883688000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-017-2144-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,20]]},"references-count":49,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2018,2]]}},"alternative-id":["2144"],"URL":"https:\/\/doi.org\/10.1007\/s11227-017-2144-1","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"type":"print","value":"0920-8542"},{"type":"electronic","value":"1573-0484"}],"subject":[],"published":{"date-parts":[[2017,9,20]]},"assertion":[{"value":"20 September 2017","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}