{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,7]],"date-time":"2026-05-07T16:30:48Z","timestamp":1778171448018,"version":"3.51.4"},"reference-count":58,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2018,11,14]],"date-time":"2018-11-14T00:00:00Z","timestamp":1542153600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2019,4]]},"DOI":"10.1007\/s11227-018-2683-0","type":"journal-article","created":{"date-parts":[[2018,11,14]],"date-time":"2018-11-14T06:10:06Z","timestamp":1542175806000},"page":"2106-2125","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":41,"title":["Design and analysis of efficient QCA reversible adders"],"prefix":"10.1007","volume":"75","author":[{"given":"Sara","family":"Hashemi","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mostafa","family":"Rahimi Azghadi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Keivan","family":"Navi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,11,14]]},"reference":[{"key":"2683_CR1","doi-asserted-by":"publisher","first-page":"525","DOI":"10.1147\/rd.176.0525","volume":"17","author":"CH Bennett","year":"1973","unstructured":"Bennett CH (1973) Logical reversibility of computation. IBM J Res Dev 17:525\u2013532","journal-title":"IBM J Res Dev"},{"key":"2683_CR2","doi-asserted-by":"publisher","first-page":"183","DOI":"10.1147\/rd.53.0183","volume":"5","author":"R Landauer","year":"1961","unstructured":"Landauer R (1961) Irreversibility and heat generation in the computational process. IBM J Res Dev 5:183\u2013191","journal-title":"IBM J Res Dev"},{"key":"2683_CR3","doi-asserted-by":"publisher","first-page":"1994","DOI":"10.1007\/s11227-017-2206-4","volume":"74","author":"SR Heikalabad","year":"2018","unstructured":"Heikalabad SR, Asfestani MN, Hosseinzadeh M (2018) A full adder structure without cross-wiring in quantum-dot cellular automata with energy dissipation analysis. J Supercomput 74:1994\u20132005","journal-title":"J Supercomput"},{"key":"2683_CR4","doi-asserted-by":"publisher","first-page":"87","DOI":"10.1007\/s11265-008-0284-5","volume":"58","author":"I H\u00e4nninen","year":"2010","unstructured":"H\u00e4nninen I, Takala J (2010) Binary adders on quantum-dot cellular automata. J Signal Process Syst 58:87\u2013103. https:\/\/doi.org\/10.1007\/s11265-008-0284-5","journal-title":"J Signal Process Syst"},{"key":"2683_CR5","doi-asserted-by":"publisher","first-page":"1818","DOI":"10.1063\/1.356375","volume":"75","author":"PD Tougaw","year":"1994","unstructured":"Tougaw PD, Lent CS (1994) Logical devices implemented using quantum cellular automata. J Appl Phys Am Inst Phys 75:1818\u20131824","journal-title":"J Appl Phys Am Inst Phys"},{"key":"2683_CR6","doi-asserted-by":"crossref","unstructured":"Wang W, Walus K, Jullien GA (2003) Quantum-dot cellular automata adders. In: Proceedings of IEEE Conference on Nanotechnology, pp 461\u2013464","DOI":"10.1109\/NANO.2003.1231818"},{"key":"2683_CR7","doi-asserted-by":"publisher","first-page":"105","DOI":"10.1109\/TNANO.2011.2158006","volume":"11","author":"V Pudi","year":"2012","unstructured":"Pudi V, Sridharan K (2012) Low complexity design of ripple carry and Brent-Kung adders in QCA. IEEE Trans Nanotechnol 11:105\u2013119","journal-title":"IEEE Trans Nanotechnol"},{"key":"2683_CR8","doi-asserted-by":"publisher","first-page":"3460","DOI":"10.3923\/jas.2007.3460.3468","volume":"7","author":"M Rahimi Azghadi","year":"2007","unstructured":"Rahimi Azghadi M, Kavehei O, Navi K (2007) A novel design for quantum-dot cellular automata cells and full-adders. J Appl Sci 7:3460\u20133468","journal-title":"J Appl Sci"},{"key":"2683_CR9","doi-asserted-by":"publisher","first-page":"376","DOI":"10.1016\/j.mspro.2015.11.133","volume":"11","author":"S Hashemi","year":"2015","unstructured":"Hashemi S, Navi K (2015) A novel robust QCA full-adder. Procedia Mater Sci 11:376\u2013380","journal-title":"Procedia Mater Sci"},{"key":"2683_CR10","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1016\/j.mejo.2016.02.004","volume":"50","author":"M Mohammadi","year":"2016","unstructured":"Mohammadi M, Mohammadi M, Gorgin S (2016) An efficient design of full adder in quantum-dot cellular automata (QCA) technology. Microelectron J 50:35\u201343","journal-title":"Microelectron J"},{"key":"2683_CR11","doi-asserted-by":"publisher","first-page":"86","DOI":"10.1016\/j.ins.2015.03.030","volume":"31","author":"S Sayedsalehi","year":"2015","unstructured":"Sayedsalehi S, Azghadi MR, Angizi S, Navi K (2015) Restoring and non-restoring array divider designs in quantum-dot cellular automata. Inf Sci 31:86\u2013101","journal-title":"Inf Sci"},{"key":"2683_CR12","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-018-2464-9","author":"SS Ahmadpour","year":"2018","unstructured":"Ahmadpour SS, Mosleh MJ (2018) A novel fault-tolerant multiplexer in quantum-dot cellular automata technology. J Supercomput. https:\/\/doi.org\/10.1007\/s11227-018-2464-9","journal-title":"J Supercomput"},{"issue":"12","key":"2683_CR13","doi-asserted-by":"publisher","first-page":"929","DOI":"10.1016\/j.mejo.2012.10.007","volume":"43","author":"S Hashemi","year":"2012","unstructured":"Hashemi S, Navi K (2012) New robust QCA D flip flop and memory structures. Microelectron J 43(12):929\u2013940","journal-title":"Microelectron J"},{"key":"2683_CR14","unstructured":"Vetteth A, Walus K, Dimitrov VS, Jullien GA (2003) Quantum-dot cellular automata of flip-flops. ATIPS Laboratory 2500 University Drive, N.W., Calgary, Alberta, Canada T2 N1N4"},{"key":"2683_CR15","doi-asserted-by":"publisher","first-page":"825","DOI":"10.1049\/el.2010.1090","volume":"46","author":"X Yang","year":"2010","unstructured":"Yang X, Cai L, Zhao X (2010) Low power dual-edge triggered flip-flop structure in quantum dot cellular automata. Electron Lett 46:825\u2013826","journal-title":"Electron Lett"},{"key":"2683_CR16","unstructured":"Murphy SF, Ottavi M, Frank M, DeBenedictis E (2006) On the design of reversible QDCA systems. Sandia National Laboratories, Albuquerque, NM, Tech. Rep. SAND2006-5990"},{"issue":"1","key":"2683_CR17","doi-asserted-by":"publisher","first-page":"62","DOI":"10.1109\/TNANO.2009.2025038","volume":"9","author":"H Thapliyal","year":"2010","unstructured":"Thapliyal H, Ranganathan N (2010) Reversible logic-based concurrently testable latches for molecular QCA. IEEE Trans Nanotechnol 9(1):62\u201369","journal-title":"IEEE Trans Nanotechnol"},{"issue":"7","key":"2683_CR18","doi-asserted-by":"publisher","first-page":"1201","DOI":"10.1109\/TVLSI.2012.2209688","volume":"21","author":"H Thapliyal","year":"2013","unstructured":"Thapliyal H, Ranganathan N, Kotiyal S (2013) Design of testable reversible sequential circuits. IEEE Trans Very Large Scale Integr (VLSI) Syst 21(7):1201\u20131209","journal-title":"IEEE Trans Very Large Scale Integr (VLSI) Syst"},{"issue":"4","key":"2683_CR19","first-page":"8","volume":"2","author":"NA Shah","year":"2012","unstructured":"Shah NA, Khanday FA, Iqbal J (2012) Quantum-dot cellular automata (QCA) design of multi-function reversible logic gate. Commun Inf Sci Manag Eng (CISME) 2(4):8\u201318","journal-title":"Commun Inf Sci Manag Eng (CISME)"},{"key":"2683_CR20","doi-asserted-by":"publisher","first-page":"523","DOI":"10.1166\/qm.2014.1158","volume":"6","author":"S Hashemi","year":"2014","unstructured":"Hashemi S, Navi K (2014) Reversible multiplexer design in quantum-dot cellular automata. Quantum Matter (ASP) 6:523\u2013528","journal-title":"Quantum Matter (ASP)"},{"key":"2683_CR21","doi-asserted-by":"publisher","first-page":"459","DOI":"10.1007\/s10825-017-0963-1","volume":"16","author":"M Kianpour","year":"2017","unstructured":"Kianpour M, Sabbaghi-Nadooshan R (2017) Novel 8-bit reversible full-adder\/subtractor using a QCA reversible gate. J Comput Electron 16:459\u2013472","journal-title":"J Comput Electron"},{"key":"2683_CR22","doi-asserted-by":"publisher","first-page":"557","DOI":"10.1016\/j.ijleo.2017.06.024","volume":"142","author":"E Taherkhani","year":"2017","unstructured":"Taherkhani E, Moaiyeri MH, Angizi S (2017) Design of an ultra-efficient reversible full adder-subtractor in quantum-dot cellular automata. Optik Int J Light Electron Opt 142:557\u2013563","journal-title":"Optik Int J Light Electron Opt"},{"key":"2683_CR23","unstructured":"Al-Shafi MA, Islam MS, Newaz Bahar A (2015) A review on reversible logic gates and it\u2019s QCA implementation. IJCA 128(2). http:\/\/www.ijcaonline.org\/archives\/volume128\/number2\/22845-2015906434"},{"issue":"1","key":"2683_CR24","doi-asserted-by":"publisher","first-page":"297","DOI":"10.1007\/s10836-007-5042-2","volume":"24","author":"X Ma","year":"2008","unstructured":"Ma X, Huang J, Metra C, Lombardi F (2008) Reversible gates and testability of one dimensional arrays of molecular QCA. J Electron Test 24(1):297\u2013311","journal-title":"J Electron Test"},{"key":"2683_CR25","doi-asserted-by":"publisher","DOI":"10.1049\/joe.2013.0177","author":"S Hashemi","year":"2014","unstructured":"Hashemi S, Navi K (2014) Designing quantum-dot cellular automata circuits using a robust one layer crossover scheme. IET J Eng. https:\/\/doi.org\/10.1049\/joe.2013.0177","journal-title":"IET J Eng"},{"key":"2683_CR26","doi-asserted-by":"publisher","first-page":"176","DOI":"10.1109\/TCAD.2006.883921","volume":"26","author":"K Kim","year":"2007","unstructured":"Kim K, Wu K, Karri R (2007) The robust QCA adder designs using composable QCA building blocks. IEEE Trans Comput Aided Des Integr Circuits Syst 26:176\u2013183","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"2683_CR27","unstructured":"Kim K, Wu K, Karri R (2005) Towards designing robust QCA architectures in the presence of sneak noise paths. In: Proceedings of the Design, Automation and Test in Europe Conference and Exhibition, pp 1214\u20131219"},{"key":"2683_CR28","doi-asserted-by":"publisher","first-page":"1234","DOI":"10.1049\/el.2009.2819","volume":"45","author":"R Devadoss","year":"2009","unstructured":"Devadoss R, Paul K, Balakrishnan M (2009) Coplanar QCA crossovers. IET Electron Lett 45:1234\u20131235","journal-title":"IET Electron Lett"},{"key":"2683_CR29","doi-asserted-by":"publisher","first-page":"215","DOI":"10.1109\/TNANO.2013.2243162","volume":"12","author":"D Tougaw","year":"2013","unstructured":"Tougaw D, Khatun M (2013) A scalable signal distribution network for quantum-dot cellular automata. IEEE Trans Nanotechnol 12:215\u2013224","journal-title":"IEEE Trans Nanotechnol"},{"key":"2683_CR30","unstructured":"Shin SH, Jeon JC, Yoo KY (2013) Wire-crossing technique on quantum-dot cellular automata. In: Second International Conference Next Generation Computer and Information Technology (NGCIT), pp 52\u201357"},{"key":"2683_CR31","doi-asserted-by":"crossref","unstructured":"Toffoli T (1980) Reversible computing. In: Proceedings of the 7th Colloquium on Automata, Languages and Programming. Springer, London, UK, pp 632\u2013644","DOI":"10.21236\/ADA082021"},{"issue":"6","key":"2683_CR32","doi-asserted-by":"publisher","first-page":"3266","DOI":"10.1103\/PhysRevA.32.3266","volume":"32","author":"A Peres","year":"1985","unstructured":"Peres A (1985) Reversible logic and quantum computers. Phys Rev A Gen Phys 32(6):3266\u20133276","journal-title":"Phys Rev A Gen Phys"},{"key":"2683_CR33","doi-asserted-by":"publisher","first-page":"219","DOI":"10.1007\/BF01857727","volume":"21","author":"E Fredkin","year":"1982","unstructured":"Fredkin E, Toffoli T (1982) Conservative logic. Int J Theor Phys 21:219\u2013253","journal-title":"Int J Theor Phys"},{"key":"2683_CR34","doi-asserted-by":"publisher","first-page":"2855","DOI":"10.1103\/PhysRevA.53.2855","volume":"53","author":"JA Smolin","year":"1996","unstructured":"Smolin JA, Divincenzo DP (1996) Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys Rev A 53:2855\u20132856","journal-title":"Phys Rev A"},{"key":"2683_CR35","unstructured":"Thapliyal H, Arabnia HR, Srinivas MB (2009) Efficient reversible logic design of BCD subtractors. In: Transactions on Computational Science Journal, Vol. III. Springer, LNCS 5300, pp 99\u2013121"},{"key":"2683_CR36","unstructured":"Thapliyal H, Arabnia HR, Bajpai R, Sharma KK (2007) Combined integer and variable precision (CIVP) floating point multiplication architecture for FPGAs. In: Proceedings of 2007 International Conference on Parallel and Distributed Processing Techniques and Applications; PDPTA\u201907, Vol 2207, USA, pp 449\u2013450"},{"key":"2683_CR37","unstructured":"Thapliyal H, Arabnia HR (2006) Reversible programmable logic array (RPLA) using Fredkin and Feynman gates for industrial electronics and applications. In: Proceedings of 2006 International Conference on Computer Design and Conference on Computing in Nanotechnology (CDES\u201906: June 26-29, 2016; Las Vegas, USA), pp 70\u201374"},{"key":"2683_CR38","unstructured":"Thapliyal H, Srinivas MB, Arabnia HR (2005) Reversible logic synthesis of half, full and parallel subtractors. In: Proceedings of 2005 international conference on embedded systems and applications, ESA\u201905, June, Las Vegas, pp 165\u2013172"},{"key":"2683_CR39","doi-asserted-by":"crossref","unstructured":"Thapliyal H, Jayashree HV, Nagamani AN, Arabnia HR (2013) Progress in reversible processor design: a novel methodology for reversible carry look-ahead adder. In: Gavrilova ML, Tan CJK (eds) Transactions in computational science (Springer), XVII, LNCS 7420. Springer, Berlin, pp 73\u201397","DOI":"10.1007\/978-3-642-35840-1_4"},{"issue":"4","key":"2683_CR40","first-page":"14","volume":"6","author":"H Thapliyal","year":"2010","unstructured":"Thapliyal H, Ranganathan N (2010) Design of reversible sequential circuits optimizing quantum cost. Delay Garbage Outputs JETC 6(4):14\u201331","journal-title":"Delay Garbage Outputs JETC"},{"key":"2683_CR41","unstructured":"Azad Khan MMH (2002) Design of full-adder with reversible gates. In: International Conference on Computer and Information Technology, Dhaka, pp 515\u2013519"},{"key":"2683_CR42","unstructured":"Khlopotine AB, Perkowski M, Kerntopf P (2002) Reversible logic synthesis by iterative composition. In: Proceedings of IWLS, 2002, pp 261\u2013266"},{"key":"2683_CR43","doi-asserted-by":"crossref","unstructured":"Bruce JW, Thornton MA, Shivakumaraiah L, Kokate PS, Li X (2002) Efficient adder circuits based on a conservative reversible logic gate. In: IEEE Computer Society Annual Symposium on VLSI, pp 74\u201379","DOI":"10.1109\/ISVLSI.2002.1016879"},{"key":"2683_CR44","unstructured":"Babu HH, Islam R, Chowdhury AR, Chowdhury SMA (2003) On the realization of reversible full-adder circuit. In: International Conference on Computer and Information Technology, Dhaka, Bangladesh, pp 880\u2013883"},{"key":"2683_CR45","doi-asserted-by":"crossref","unstructured":"Babu HMH, Islam MR, Chowdhury AR, Chowdhury SMA (2003) Reversible logic synthesis for minimization of full adder circuit. In Proceedings of the Euro Micro Symposium on Digital System Design (DSD\u201d03), Belek-Antalya, Turkey, pp 50\u201354","DOI":"10.1109\/DSD.2003.1231899"},{"key":"2683_CR46","doi-asserted-by":"crossref","unstructured":"Thapliyal H, Srinivas MB (2005) A novel reversible TSG gate and its application for designing reversible carry look-ahead and other adder architectures. In: Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture (ACSAC\u201d05), pp 805\u2013817","DOI":"10.1007\/11572961_66"},{"key":"2683_CR47","doi-asserted-by":"crossref","unstructured":"Thapliyal H, Srinivas MB (2005) Novel design and reversible logic synthesis of multiplexer based full adder and multipliers. In: 48th Midwest Symposium on Circuits and Systems, vol 2, pp 1593\u20131596","DOI":"10.1109\/MWSCAS.2005.1594420"},{"issue":"12","key":"2683_CR48","first-page":"1146","volume":"4","author":"S Islam","year":"2005","unstructured":"Islam S, Islam R (2005) Minimization of reversible adder circuits. Asian J Inf Technol 4(12):1146\u20131151","journal-title":"Asian J Inf Technol"},{"key":"2683_CR49","doi-asserted-by":"publisher","first-page":"272","DOI":"10.1016\/j.sysarc.2005.05.005","volume":"52","author":"HMH Babu","year":"2006","unstructured":"Babu HMH, Chowdhury AR (2006) Design of a compact reversible binary coded decimal adder circuit. J Syst Archit 52:272\u2013282","journal-title":"J Syst Archit"},{"key":"2683_CR50","doi-asserted-by":"crossref","unstructured":"Thapliyal H, Vinod AP (2007) Designing efficient online testable reversible adders with new reversible gate. In: Proceedings of ISCAS 2007, New Orleans, USA, pp 1085\u20131088","DOI":"10.1109\/ISCAS.2007.378198"},{"key":"2683_CR51","doi-asserted-by":"crossref","first-page":"3995","DOI":"10.3923\/jas.2007.3995.4000","volume":"7","author":"M Haghparasat","year":"2008","unstructured":"Haghparasat M, Navi K (2008) A novel reversible full adder circuit for nanotechnology based systems. J Appl Sci 7:3995\u20134000","journal-title":"J Appl Sci"},{"issue":"3","key":"2683_CR52","doi-asserted-by":"publisher","first-page":"282","DOI":"10.3844\/ajassp.2008.282.288","volume":"5","author":"M Haghparast","year":"2008","unstructured":"Haghparast M, Navi K (2008) A novel reversible BCD adder for nanotechnology based systems. Am J Appl Sci 5(3):282\u2013288","journal-title":"Am J Appl Sci"},{"key":"2683_CR53","unstructured":"Saiful Islam M (2009) A novel quantum cost efficient reversible full adder gate in nanotechnology. http:\/\/arxiv.org\/abs\/1008.3533"},{"key":"2683_CR54","doi-asserted-by":"crossref","unstructured":"Ni L, Guan Z, Zhu W (2010) A general method of constructing the reversible full-adder. In: Third International Symposium on Intelligent Information Technology and Security Informatics (IITSI), pp 109\u2013113","DOI":"10.1109\/IITSI.2010.25"},{"key":"2683_CR55","first-page":"30","volume":"31","author":"D Sengupta","year":"2011","unstructured":"Sengupta D, Sultana M, Chaudhuri A (2011) Realization of a novel reversible SCG gate and its application for designing parallel adder\/subtractor and match logic. Int J Comput Appl 31:30\u201335","journal-title":"Int J Comput Appl"},{"key":"2683_CR56","doi-asserted-by":"crossref","first-page":"623","DOI":"10.1007\/978-3-642-31600-5_61","volume":"178","author":"AV AnanthaLakshmi","year":"2013","unstructured":"AnanthaLakshmi AV, Sudha GF (2013) Design of a novel reversible full adder and reversible full subtractor. Adv Intell Syst Comput 178:623\u2013632","journal-title":"Adv Intell Syst Comput"},{"key":"2683_CR57","doi-asserted-by":"crossref","unstructured":"Kunalan D, Cheong CL, Chau CF, Ghazali AB (2014) Design of a 4-bit adder using reversible logic in quantum-dot cellular automata (QCA). In: Proceedings of IEEE-ICSE2014, Kuala Lumpur","DOI":"10.1109\/SMELEC.2014.6920795"},{"key":"2683_CR58","doi-asserted-by":"publisher","first-page":"2127","DOI":"10.1007\/s11128-014-0782-2","volume":"13","author":"Z Mohammadi","year":"2014","unstructured":"Mohammadi Z, Mohammadi M (2014) Implementing a one-bit reversible full adder using quantum-dot cellular automata. Quantum Inf Process 13:2127\u20132147","journal-title":"Quantum Inf Process"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-018-2683-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11227-018-2683-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-018-2683-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,7]],"date-time":"2023-09-07T02:07:19Z","timestamp":1694052439000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11227-018-2683-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,11,14]]},"references-count":58,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2019,4]]}},"alternative-id":["2683"],"URL":"https:\/\/doi.org\/10.1007\/s11227-018-2683-0","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,11,14]]},"assertion":[{"value":"14 November 2018","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}