{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,2]],"date-time":"2026-04-02T01:46:36Z","timestamp":1775094396818,"version":"3.50.1"},"reference-count":51,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T00:00:00Z","timestamp":1626825600000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T00:00:00Z","timestamp":1626825600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springer.com\/tdm"}],"funder":[{"name":"Industry-University-Research Cooperation Fund","award":["SAST2020-068"],"award-info":[{"award-number":["SAST2020-068"]}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation","doi-asserted-by":"crossref","award":["61872017"],"award-info":[{"award-number":["61872017"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation","doi-asserted-by":"crossref","award":["61803034"],"award-info":[{"award-number":["61803034"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2022,2]]},"DOI":"10.1007\/s11227-021-03909-y","type":"journal-article","created":{"date-parts":[[2021,7,21]],"date-time":"2021-07-21T11:14:27Z","timestamp":1626866067000},"page":"3205-3225","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["High-efficient MPSoC-based CNNs accelerator with optimized storage and dataflow"],"prefix":"10.1007","volume":"78","author":[{"given":"Yonghua","family":"Zhang","sequence":"first","affiliation":[]},{"given":"Hongxu","family":"Jiang","sequence":"additional","affiliation":[]},{"given":"Xiaojian","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Haiheng","family":"Cao","sequence":"additional","affiliation":[]},{"given":"Yu","family":"Du","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2021,7,21]]},"reference":[{"key":"3909_CR1","doi-asserted-by":"crossref","unstructured":"Szegedy C, Liu W, Jia Y, Sermanet P, Reed S, Anguelov D, Erhan D, Vanhoucke V, Rabinovich A (2015). Going deeper with convolutions. Paper presented at the Proceedings of the IEEE conference on computer vision and pattern recognition (pp. 1\u20139)","DOI":"10.1109\/CVPR.2015.7298594"},{"issue":"6","key":"3909_CR2","doi-asserted-by":"publisher","first-page":"2529","DOI":"10.1109\/TIP.2016.2547588","volume":"25","author":"T He","year":"2016","unstructured":"He T, Huang W, Qiao Y, Yao J (2016) Text-attentional convolutional neural network for scene text detection. IEEE Trans Image Process 25(6):2529\u20132541","journal-title":"IEEE Trans Image Process"},{"key":"3909_CR3","doi-asserted-by":"crossref","unstructured":"Li H, Lin Z, Shen X, Brandt J, Hua G (2015) A convolutional neural network cascade for face detection. In Proceedings of the IEEE conference on computer vision and pattern recognition (pp. 5325\u20135334)","DOI":"10.1109\/CVPR.2015.7299170"},{"key":"3909_CR4","doi-asserted-by":"publisher","first-page":"482","DOI":"10.1016\/j.image.2016.05.007","volume":"47","author":"D Tom\u00e8","year":"2016","unstructured":"Tom\u00e8 D, Monti F, Baroffio L, Bondi L, Tagliasacchi M, Tubaro S (2016) Deep convolutional neural networks for pedestrian detection. Signal Process Image Commun 47:482\u2013489","journal-title":"Signal Process Image Commun"},{"key":"3909_CR5","unstructured":"Amodei D, Ananthanarayanan S, Anubhai R, Bai J, Battenberg E, Case C, Casper J, Catanzaro B, Cheng Q, Chen G (2016, June). Deep speech 2: End-to-end speech recognition in english and mandarin. In International conference on machine learning (pp. 173\u2013182)"},{"issue":"3","key":"3909_CR6","doi-asserted-by":"publisher","first-page":"243","DOI":"10.1145\/3007787.3001163","volume":"44","author":"S Han","year":"2016","unstructured":"Han S, Liu X, Mao H, Pu J, Pedram A, Horowitz MA, Dally WJ (2016) EIE: efficient inference engine on compressed deep neural network. ACM SIGARCH Comput Archit News 44(3):243\u2013254","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"3909_CR7","doi-asserted-by":"crossref","unstructured":"Zhang S, Du Z, Zhang L, Lan H, Liu S, Li L, Guo Q, Chen T, Chen Y (2016) Cambricon-x: An accelerator for sparse neural networks. In 2016 49th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO) (pp. 1\u201312)","DOI":"10.1109\/MICRO.2016.7783723"},{"issue":"3","key":"3909_CR8","doi-asserted-by":"publisher","first-page":"367","DOI":"10.1145\/3007787.3001177","volume":"44","author":"YH Chen","year":"2016","unstructured":"Chen YH, Emer J, Sze V (2016) Eyeriss: A spatial architecture for energy-efficient dataflow for convolutional neural networks. ACM SIGARCH Comput Archit News 44(3):367\u2013379","journal-title":"ACM SIGARCH Comput Archit News"},{"key":"3909_CR9","doi-asserted-by":"crossref","unstructured":"Du Z, Fasthuber R, Chen T, Ienne P, Li L, Luo T, Feng X, Chen Y, Temam O (2015) ShiDianNao: Shifting vision processing closer to the sensor. In Proceedings of the 42nd Annual International Symposium on Computer Architecture (pp. 92\u2013104)","DOI":"10.1145\/2749469.2750389"},{"issue":"1","key":"3909_CR10","doi-asserted-by":"publisher","first-page":"369","DOI":"10.1145\/2786763.2694358","volume":"43","author":"D Liu","year":"2015","unstructured":"Liu D, Chen T, Liu S, Zhou J, Zhou S, Teman O, Feng X, Zhou X, Chen YJ (2015) Pudiannao: A polyvalent machine learning accelerator. ACM SIGARCH Comput Archit News 43(1):369\u2013381","journal-title":"ACM SIGARCH Comput Archit News"},{"issue":"3","key":"3909_CR11","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/MM.2015.41","volume":"35","author":"T Chen","year":"2015","unstructured":"Chen T, Du Z, Sun N, Wang J, Wu C, Chen Y, Temam O (2015) A high-throughput neural network accelerator. IEEE Micro 35(3):24\u201332","journal-title":"IEEE Micro"},{"key":"3909_CR12","doi-asserted-by":"crossref","unstructured":"Mei C, Liu Z, Niu Y, Ji X, Zhou W, Wang D (2017) A 200mhz 202.4 gflops@ 10.8 w vgg16 accelerator in xilinx vx690t. In 2017 IEEE Global Conference on Signal and Information Processing (GlobalSIP) (pp. 784\u2013788)","DOI":"10.1109\/GlobalSIP.2017.8309067"},{"key":"3909_CR13","doi-asserted-by":"crossref","unstructured":"Ma J, Chen L, Gao Z (2017) Hardware implementation and optimization of tiny-yolo network. In International Forum on Digital TV and Wireless Multimedia Communications (pp. 224\u2013234).","DOI":"10.1007\/978-981-10-8108-8_21"},{"issue":"10","key":"3909_CR14","first-page":"506","volume":"9","author":"YJ Wai","year":"2018","unstructured":"Wai YJ, Bin Mohd Yussof Z, Bin Salim SI, Chuan LK (2018) Fixed point implementation of tiny-yolo-v2 using opencl on fpga. Int J Adv Comput Sci Appl 9(10):506\u2013512","journal-title":"Int J Adv Comput Sci Appl"},{"issue":"1","key":"3909_CR15","doi-asserted-by":"publisher","first-page":"127","DOI":"10.1109\/JSSC.2016.2616357","volume":"52","author":"YH Chen","year":"2016","unstructured":"Chen YH, Krishna T, Emer JS, Sze V (2016) Eyeriss: An energy-efficient reconfigurable accelerator for deep convolutional neural networks. IEEE J Solid-State Circuits 52(1):127\u2013138","journal-title":"IEEE J Solid-State Circuits"},{"issue":"1","key":"3909_CR16","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/TCAD.2017.2705069","volume":"37","author":"K Guo","year":"2018","unstructured":"Guo K, Sui L, Qiu J, Yu J, Wang J, Yao S, Han S, Wang Y, Yang HZ (2018) Angel-eye: a complete design flow for mapping CNN onto embedded FPGA. IEEE Trans Comput Aided Des Integr Circuits Syst 37(1):35\u201347","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"3909_CR17","doi-asserted-by":"publisher","first-page":"198","DOI":"10.1109\/TCSI.2017.2735490","volume":"65","author":"L Du","year":"2017","unstructured":"Du L, Du Y, Li Y, Su J, Kuan YC, Liu CC, Chang MCF (2017) A reconfigurable streaming deep convolutional neural network accelerator for Internet of Things. IEEE Trans Circuits Syst I Regul Pap 65(1):198\u2013208","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"6","key":"3909_CR18","doi-asserted-by":"publisher","first-page":"1941","DOI":"10.1109\/TCSI.2017.2767204","volume":"65","author":"J Wang","year":"2017","unstructured":"Wang J, Lin J, Wang Z (2017) Efficient hardware architectures for deep convolutional neural network. IEEE Trans Circuits Syst I Regul Pap 65(6):1941\u20131953","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"7","key":"3909_CR19","doi-asserted-by":"publisher","first-page":"1354","DOI":"10.1109\/TVLSI.2018.2815603","volume":"26","author":"MY Ma","year":"2018","unstructured":"Ma MY, Cao Y, Vrudhula S, Seo JS (2018) Optimizing the convolution operation to accelerate deep neural networks on FPGA. IEEE Trans Very Large Scale Integr VLSI Syst 26(7):1354\u20131367","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"12","key":"3909_CR20","doi-asserted-by":"publisher","first-page":"5922","DOI":"10.1109\/TNNLS.2018.2815085","volume":"29","author":"N Shah","year":"2018","unstructured":"Shah N, Chaudhari P, Varghese K (2018) Runtime programmable and memory bandwidth optimized FPGA-based coprocessor for deep convolutional neural network. IEEE Trans Neural Netw Learn Syst 29(12):5922\u20135934","journal-title":"IEEE Trans Neural Netw Learn Syst"},{"issue":"5","key":"3909_CR21","doi-asserted-by":"publisher","first-page":"1642","DOI":"10.1109\/TCSI.2017.2759803","volume":"65","author":"YJ Lin","year":"2017","unstructured":"Lin YJ, Chang TS (2017) Data and hardware efficient design for convolutional neural network. IEEE Trans Circuits Syst I Regul Pap 65(5):1642\u20131651","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"12","key":"3909_CR22","doi-asserted-by":"publisher","first-page":"4196","DOI":"10.1109\/TCSI.2018.2840092","volume":"65","author":"J Jo","year":"2018","unstructured":"Jo J, Kim S, Park IC (2018) Energy-efficient convolution architecture based on rescheduled dataflow. IEEE Trans Circuits Syst I Regul Pap 65(12):4196\u20134207","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"3909_CR23","doi-asserted-by":"crossref","unstructured":"Qiu J, Wang J, Yao S, Guo K, Li B, Zhou E, Yu J, Tang T, Xu N, Song S (2016) Going deeper with embedded fpga platform for convolutional neural network. In Proceedings of the 2016 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 26\u201335).","DOI":"10.1145\/2847263.2847265"},{"key":"3909_CR24","doi-asserted-by":"crossref","unstructured":"Wang S, Zhou D, Han X, Yoshimura T (2017) Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks. In Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017 (pp. 1032\u20131037)","DOI":"10.23919\/DATE.2017.7927142"},{"key":"3909_CR25","doi-asserted-by":"crossref","unstructured":"Shi R, Xu Z, Sun Z, Peemen M, Li A, Corporaal H, Wu D (2015). A locality aware convolutional neural networks accelerator. In 2015 Euromicro Conference on Digital System Design (pp. 591\u2013598)","DOI":"10.1109\/DSD.2015.70"},{"key":"3909_CR26","doi-asserted-by":"crossref","unstructured":"Xin C, Chen Q, Tian M, Ji M, Zou C, Wang B (2017) COSY: an energy-efficient hardware architecture for deep convolutional neural networks based on systolic array. In 2017 IEEE 23rd International Conference on Parallel and Distributed Systems (ICPADS) (pp. 180\u2013189)","DOI":"10.1109\/ICPADS.2017.00034"},{"key":"3909_CR27","doi-asserted-by":"crossref","unstructured":"Xiao Q, Liang Y, Lu L, Yan S, Tai Y W (2017) Exploring heterogeneous algorithms for accelerating deep convolutional neural networks on FPGAs. In Proceedings of the 54th Annual Design Automation Conference 2017 (pp. 1\u20136)","DOI":"10.1145\/3061639.3062244"},{"issue":"5","key":"3909_CR28","doi-asserted-by":"publisher","first-page":"1037","DOI":"10.1587\/transinf.2018RCP0008","volume":"102","author":"C Luo","year":"2019","unstructured":"Luo C, Cao W, Wang L, Leong PH (2019) Rna: an accurate residual network accelerator for quantized and reconstructed deep neural networks. IEICE Trans Inf Syst 102(5):1037\u20131045","journal-title":"IEICE Trans Inf Syst"},{"key":"3909_CR29","doi-asserted-by":"crossref","unstructured":"Li J, Yan G, Lu W, Jiang S, Gong S, Wu J, Li X (2018) SmartShuttle: Optimizing off-chip memory accesses for deep learning accelerators. In 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 343\u2013348)","DOI":"10.23919\/DATE.2018.8342033"},{"key":"3909_CR30","doi-asserted-by":"crossref","unstructured":"Song L, Wang Y, Han Y, Zhao X, Liu B, Li X (2016) C-Brain: a deep learning accelerator that tames the diversity of CNNs through adaptive data-level parallelization. In Proceedings of the 53rd Annual Design Automation Conference (pp. 1\u20136)","DOI":"10.1145\/2897937.2897995"},{"key":"3909_CR31","doi-asserted-by":"crossref","unstructured":"Lu W, Yan G, Li J, Gong S, Han Y, Li X (2017) Flexflow: a flexible dataflow accelerator architecture for convolutional neural networks. In 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA) (pp. 553\u2013564)","DOI":"10.1109\/HPCA.2017.29"},{"key":"3909_CR32","doi-asserted-by":"crossref","unstructured":"Liu B, Chen X, Wang Y, Han Y, Li J, Xu H, Li X (2019) Addressing the issue of processing element under-utilization in general-purpose systolic deep learning accelerators. In Proceedings of the 24th Asia and South Pacific Design Automation Conference (pp. 733\u2013738)","DOI":"10.1145\/3287624.3287638"},{"key":"3909_CR33","doi-asserted-by":"crossref","unstructured":"Zhang C, Li P, Sun G, Guan Y, Xiao B, Cong J (2015) Optimizing fpga-based accelerator design for deep convolutional neural networks. In Proceedings of the 2015 ACM\/SIGDA international symposium on field-programmable gate arrays (pp. 161\u2013170)","DOI":"10.1145\/2684746.2689060"},{"key":"3909_CR34","doi-asserted-by":"crossref","unstructured":"Yang K, Wang S, Zhou J, Yoshimura T (2017) Energy-efficient scheduling method with cross-loop model for resource-limited CNN accelerator designs. In 2017 IEEE International Symposium on Circuits and Systems (ISCAS) (pp. 1\u20134)","DOI":"10.1109\/ISCAS.2017.8050800"},{"key":"3909_CR35","unstructured":"Yang X, Pu J, Rister B B, Bhagdikar N, Richardson S, Kvatinsky S, Ragan-Kelley J, Pedram A, Horowitz M (2016). A systematic approach to blocking convolutional neural networks. arXiv preprint"},{"key":"3909_CR36","doi-asserted-by":"crossref","unstructured":"Peemen M, Mesman B, Corporaal H (2015). Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators. In 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE) (pp. 169\u2013174)","DOI":"10.7873\/DATE.2015.1033"},{"key":"3909_CR37","doi-asserted-by":"crossref","unstructured":"Ma Y, Cao Y, Vrudhula S, Seo J S (2017) Optimizing loop operation and dataflow in FPGA acceleration of deep convolutional neural networks. In Proceedings of the 2017 ACM\/SIGDA International Symposium on Field-Programmable Gate Arrays (pp. 45\u201354)","DOI":"10.1145\/3020078.3021736"},{"key":"3909_CR38","doi-asserted-by":"crossref","unstructured":"Motamedi M, Gysel P, Akella V, Ghiasi S (2016) Design space exploration of FPGA-based deep convolutional neural networks. In 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC) (pp. 575\u2013580)","DOI":"10.1109\/ASPDAC.2016.7428073"},{"key":"3909_CR39","doi-asserted-by":"crossref","unstructured":"Wei X, Yu C H, Zhang P, Chen Y, Wang Y, Hu H, Liang Y, Cong J (2017) Automated systolic array architecture synthesis for high throughput CNN inference on FPGAs. In Proceedings of the 54th Annual Design Automation Conference 2017 (pp. 1\u20136)","DOI":"10.1145\/3061639.3062207"},{"key":"3909_CR40","doi-asserted-by":"crossref","unstructured":"Venieris S I, Bouganis C S (2016) fpgaConvNet: a framework for mapping convolutional neural networks on FPGAs. In 2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 40\u201347)","DOI":"10.1109\/FCCM.2016.22"},{"issue":"2","key":"3909_CR41","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/MM.2017.39","volume":"37","author":"K Guo","year":"2017","unstructured":"Guo K, Han S, Yao S, Wang Y, Xie Y, Yang H (2017) Software-hardware codesign for efficient neural network acceleration. IEEE Micro 37(2):18\u201325","journal-title":"IEEE Micro"},{"issue":"1","key":"3909_CR42","doi-asserted-by":"publisher","first-page":"35","DOI":"10.1109\/TVLSI.2019.2939726","volume":"28","author":"Y Yu","year":"2019","unstructured":"Yu Y, Wu C, Zhao T, Wang K, He L (2019) Opu: An fpga-based overlay processor for convolutional neural networks. IEEE Trans Very Large Scale Integr VLSI Syst 28(1):35\u201347","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"11","key":"3909_CR43","doi-asserted-by":"publisher","first-page":"1332","DOI":"10.1109\/TCSII.2017.2691771","volume":"64","author":"Y Choi","year":"2017","unstructured":"Choi Y, Bae D, Sim J, Choi S, Kim M, Kim LS (2017) Energy-efficient design of processing element for convolutional neural network. IEEE Trans Circuits Syst II Express Briefs 64(11):1332\u20131336","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"issue":"8","key":"3909_CR44","doi-asserted-by":"publisher","first-page":"1874","DOI":"10.1109\/TVLSI.2019.2913958","volume":"27","author":"X Lian","year":"2019","unstructured":"Lian X, Liu Z, Song Z, Dai J, Zhou W, Ji X (2019) High-performance fpga-based cnn accelerator with block-floating-point arithmetic. IEEE Trans Very Large Scale Integr VLSI Syst 27(8):1874\u20131885","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"key":"3909_CR45","doi-asserted-by":"crossref","unstructured":"Cong J, Xiao B (2014) Minimizing computation in convolutional neural networks. In International conference on artificial neural networks (pp. 281\u2013290)","DOI":"10.1007\/978-3-319-11179-7_36"},{"key":"3909_CR46","unstructured":"Krizhevsky A, Sutskever I, Hinton G E (2012) Imagenet classification with deep convolutional neural networks. In Advances in neural information processing systems (pp. 1097\u20131105)"},{"key":"3909_CR47","unstructured":"Simonyan K, Zisserman A (2014). Very deep convolutional networks for large-scale image recognition. arXiv preprint"},{"key":"3909_CR48","unstructured":"Iandola F N, Han S, Moskewicz M W, Ashraf K, Dally W J, Keutzer K (2016). SqueezeNet: AlexNet-level accuracy with 50x fewer parameters and< 0.5 MB model size. arXiv preprint"},{"key":"3909_CR49","doi-asserted-by":"crossref","unstructured":"He K, Zhang X, Ren S, Sun J (2016) Deep residual learning for image recognition. In Proceedings of the IEEE conference on computer vision and pattern recognition (pp. 770\u2013778)","DOI":"10.1109\/CVPR.2016.90"},{"issue":"11","key":"3909_CR50","doi-asserted-by":"publisher","first-page":"5784","DOI":"10.1109\/TNNLS.2018.2808319","volume":"29","author":"P Gysel","year":"2018","unstructured":"Gysel P, Pimentel J, Motamedi M, Ghiasi S (2018) Ristretto: a framework for empirical study of resource-efficient inference in convolutional neural networks. IEEE Trans Neural Netw Learn Syst 29(11):5784\u20135789","journal-title":"IEEE Trans Neural Netw Learn Syst"},{"key":"3909_CR51","unstructured":"Fu Y, Wu E, Sirasao A, Attia S, Khan K, Wittig R (2016). Deep learning with int8 optimization on xilinx devices. White Paper."}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-021-03909-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11227-021-03909-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-021-03909-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,7]],"date-time":"2022-02-07T13:11:26Z","timestamp":1644239486000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11227-021-03909-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,7,21]]},"references-count":51,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2022,2]]}},"alternative-id":["3909"],"URL":"https:\/\/doi.org\/10.1007\/s11227-021-03909-y","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,7,21]]},"assertion":[{"value":"22 May 2021","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 July 2021","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}