{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T16:27:57Z","timestamp":1779380877032,"version":"3.53.1"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"14","license":[{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T00:00:00Z","timestamp":1717200000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"name":"National Key R&D Program, China","award":["2022YFB4401401"],"award-info":[{"award-number":["2022YFB4401401"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2024,9]]},"DOI":"10.1007\/s11227-024-06261-z","type":"journal-article","created":{"date-parts":[[2024,6,1]],"date-time":"2024-06-01T06:02:42Z","timestamp":1717221762000},"page":"20488-20517","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":1,"title":["ETRS: efficient turn restrictions setting method for boundary routers in chiplet-based systems"],"prefix":"10.1007","volume":"80","author":[{"given":"Zhipeng","family":"Cao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wei","family":"Guo","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zhiquan","family":"Wan","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Peijie","family":"Li","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Qinrang","family":"Liu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Caining","family":"Wang","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yangxue","family":"Shao","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2024,6,1]]},"reference":[{"issue":"11","key":"6261_CR1","doi-asserted-by":"publisher","first-page":"2424","DOI":"10.1109\/TVLSI.2020.3015494","volume":"28","author":"J Kim","year":"2020","unstructured":"Kim J, Murali G, Park H, Qin E, Kwon H, Chekuri VCK, Rahman NM, Dasari N, Singh A, Lee M (2020) Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse. IEEE Trans Very Large Scale Integr VLSI Syst 28(11):2424\u20132437","journal-title":"IEEE Trans Very Large Scale Integr VLSI Syst"},{"issue":"12","key":"6261_CR2","doi-asserted-by":"publisher","first-page":"5183","DOI":"10.1109\/TCAD.2020.2970019","volume":"39","author":"A Coskun","year":"2020","unstructured":"Coskun A, Eris F, Joshi A, Kahng AB, Ma Y, Narayan A, Srinivas V (2020) Cross-layer co-optimization of network design and chiplet placement in 2.5-D systems. IEEE Trans Comput Aided Des Integr Circuits Syst 39(12):5183\u20135196","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"6261_CR3","doi-asserted-by":"publisher","first-page":"43","DOI":"10.1007\/s42514-022-00093-0","volume":"4","author":"X Ma","year":"2022","unstructured":"Ma X, Wang Y, Wang Y, Cai X, Han Y (2022) Survey on chiplets: interface, interconnect and integration methodology. CCF Trans High Perform Comput 4(1):43\u201352","journal-title":"CCF Trans High Perform Comput"},{"issue":"9","key":"6261_CR4","doi-asserted-by":"publisher","first-page":"1423","DOI":"10.1109\/TCPMT.2022.3207195","volume":"12","author":"DD Sharma","year":"2022","unstructured":"Sharma DD, Pasdast G, Qian Z, Aygun K (2022) Universal chiplet interconnect express (UCIe): an open industry standard for innovations with chiplets at package level. IEEE Trans Compon Packag Manuf Technol 12(9):1423\u20131431","journal-title":"IEEE Trans Compon Packag Manuf Technol"},{"key":"6261_CR5","doi-asserted-by":"crossref","unstructured":"Naffziger S, Beck N, Burd T, Lepak K, Loh GH, Subramony M, White S (2021) Pioneering chiplet technology and design for the amd epyc$$^{{\\rm TM}}$$ and ryzen$$^{{\\rm TM}}$$ processor families: industrial product. In: 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA). IEEE, pp 57\u201370","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"6261_CR6","doi-asserted-by":"crossref","unstructured":"Nassif N, Munch AO, Molnar CL, Pasdast G, Lyer SV, Yang Z, Mendoza O, Huddart M, Venkataraman S, Kandula S (2022) Sapphire rapids: the next-generation intel xeon scalable processor. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), vol 65. IEEE, pp 44\u201346","DOI":"10.1109\/ISSCC42614.2022.9731107"},{"key":"6261_CR7","volume-title":"Principles and practices of interconnection networks","author":"WJ Dally","year":"2004","unstructured":"Dally WJ, Towles BP (2004) Principles and practices of interconnection networks. Elsevier, San Francisco"},{"key":"6261_CR8","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-01755-1","volume-title":"On-chip networks","author":"NDE Jerger","year":"2017","unstructured":"Jerger NDE, Krishna T, Peh L-S, Martonosi M (2017) On-chip networks, vol 12. Springer, Geneva"},{"key":"6261_CR9","doi-asserted-by":"crossref","unstructured":"Yin J, Lin Z, Kayiran O, Poremba M, Altaf MSB, Jerger NE, Loh GH (2018) Modular routing design for chiplet-based systems. In: 2018 ACM\/IEEE 45th Annual International Symposium on Computer Architecture (ISCA). IEEE, pp 726\u2013738","DOI":"10.1109\/ISCA.2018.00066"},{"key":"6261_CR10","doi-asserted-by":"crossref","unstructured":"Cao W, Jiang S, Huang L (2022) Fast turn restriction algorithm to build deadlock-free modular chiplet integration systems. In: 2022 IEEE 4th International Conference on Circuits and Systems (ICCS). IEEE, pp 27\u201332","DOI":"10.1109\/ICCS56666.2022.9936469"},{"issue":"6","key":"6261_CR11","doi-asserted-by":"publisher","first-page":"99","DOI":"10.1109\/MDAT.2022.3203005","volume":"39","author":"C Chen","year":"2022","unstructured":"Chen C, Yin J, Peng Y, Palesi M, Cao W, Huang L, Singh AK, Zhi H, Wang X (2022) Design challenges of intra-and inter-chiplet interconnection. IEEE Des Test 39(6):99\u2013109","journal-title":"IEEE Des Test"},{"key":"6261_CR12","doi-asserted-by":"crossref","unstructured":"Wu Y, Wang L, Wang X, Han J, Zhu J, Jiang H, Yin S, Wei S, Liu L (2022) Upward packet popup for deadlock freedom in modular chiplet-based systems. In: 2022 IEEE International Symposium on High-Performance Computer Architecture (HPCA). IEEE, pp 986\u20131000","DOI":"10.1109\/HPCA53966.2022.00076"},{"issue":"11","key":"6261_CR13","doi-asserted-by":"publisher","first-page":"1928","DOI":"10.1109\/TC.2020.3029682","volume":"70","author":"P Majumder","year":"2020","unstructured":"Majumder P, Kim S, Huang J, Yum KH, Kim EJ (2020) Remote control: a simple deadlock avoidance scheme for modular systems-on-chip. IEEE Trans Comput 70(11):1928\u20131941","journal-title":"IEEE Trans Comput"},{"key":"6261_CR14","doi-asserted-by":"crossref","unstructured":"Woeginger GJ (2003) Exact algorithms for np-hard problems: a survey. In: Combinatorial Optimization-Eureka, You Shrink! Papers Dedicated to Jack Edmonds 5th International Workshop Aussois, France, 5\u20139 Mar, 2001 Revised Papers. Springer, pp 185\u2013207","DOI":"10.1007\/3-540-36478-1_17"},{"issue":"2","key":"6261_CR15","doi-asserted-by":"publisher","first-page":"182","DOI":"10.1109\/4235.996017","volume":"6","author":"K Deb","year":"2002","unstructured":"Deb K, Pratap A, Agarwal S, Meyarivan T (2002) A fast and elitist multiobjective genetic algorithm: NSGA-II. IEEE Trans Evol Comput 6(2):182\u2013197","journal-title":"IEEE Trans Evol Comput"},{"issue":"4","key":"6261_CR16","doi-asserted-by":"publisher","first-page":"670","DOI":"10.3390\/electronics9040670","volume":"9","author":"T Li","year":"2020","unstructured":"Li T, Hou J, Yan J, Liu R, Yang H, Sun Z (2020) Chiplet heterogeneous integration technology-status and challenges. Electronics 9(4):670\u2013682","journal-title":"Electronics"},{"issue":"2","key":"6261_CR17","doi-asserted-by":"publisher","first-page":"205","DOI":"10.3390\/mi13020205","volume":"13","author":"G Shan","year":"2022","unstructured":"Shan G, Zheng Y, Xing C, Chen D, Li G, Yang Y (2022) Architecture of computing system based on chiplet. Micromachines 13(2):205\u2013223","journal-title":"Micromachines"},{"key":"6261_CR18","doi-asserted-by":"crossref","unstructured":"Pal S, Liu J, Alam I, Cebry N, Suhail H, Bu S, Iyer SS, Pamarti S, Kumar R, Gupta P (2021) Designing a 2048-chiplet, 14336-core waferscale processor. In: 2021 58th ACM\/IEEE Design Automation Conference (DAC). IEEE, pp 1183\u20131188","DOI":"10.1109\/DAC18074.2021.9586194"},{"issue":"5","key":"6261_CR19","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1109\/MM.2021.3085578","volume":"41","author":"J Xia","year":"2021","unstructured":"Xia J, Cheng C, Zhou X, Hu Y, Chun P (2021) Kunpeng 920: the first 7-nm chiplet-based 64-core arm soc for cloud services. IEEE Micro 41(5):67\u201375","journal-title":"IEEE Micro"},{"key":"6261_CR20","doi-asserted-by":"crossref","unstructured":"Naffziger S, Lepak K, Paraschou M, Subramony M (2020) 2.2 AMD chiplet architecture for high-performance server and desktop products. In: 2020 IEEE International Solid-State Circuits Conference-(ISSCC). IEEE, pp 44\u201345","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"issue":"2","key":"6261_CR21","doi-asserted-by":"publisher","first-page":"63","DOI":"10.1109\/MM.2020.2976067","volume":"40","author":"M Wade","year":"2020","unstructured":"Wade M, Anderson E, Ardalan S, Bhargava P, Buchbinder S, Davenport ML, Fini J, Lu H, Li C, Meade R (2020) Teraphy: a chiplet technology for low-power, high-bandwidth in-package optical I\/O. IEEE Micro 40(2):63\u201371","journal-title":"IEEE Micro"},{"key":"6261_CR22","doi-asserted-by":"crossref","unstructured":"Taheri E, Pasricha S, Nikdast M (2022) Deft: a deadlock-free and fault-tolerant routing algorithm for 2.5 D chiplet networks. In: 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, pp 1047\u20131052","DOI":"10.23919\/DATE54114.2022.9774617"},{"key":"6261_CR23","doi-asserted-by":"crossref","unstructured":"Stow D, Xie Y, Siddiqua T, Loh GH (2017) Cost-effective design of scalable high-performance systems using active and passive interposers. In: 2017 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD). IEEE, pp 728\u2013735","DOI":"10.1109\/ICCAD.2017.8203849"},{"key":"6261_CR24","doi-asserted-by":"publisher","first-page":"547","DOI":"10.1109\/TC.1987.1676939","volume":"100","author":"WJ Dally","year":"1987","unstructured":"Dally WJ, Seitz CL (1987) Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans Comput 100:547\u2013553","journal-title":"IEEE Trans Comput"},{"key":"6261_CR25","doi-asserted-by":"publisher","DOI":"10.1016\/j.vlsi.2024.102149","volume":"96","author":"Z Cao","year":"2024","unstructured":"Cao Z, Wan Z, Li P, Liu Q, Wang C, Shao Y (2024) Lbdr: A load-balanced deadlock-free routing strategy for chiplet systems. Integration 96:102149","journal-title":"Integration"},{"key":"6261_CR26","doi-asserted-by":"crossref","unstructured":"Goldberg EI, Prasad MR, Brayton RK (2002) Using problem symmetry in search based satisfiability algorithms. In: Proceedings 2002 Design, Automation and Test in Europe Conference and Exhibition. IEEE, pp 134\u2013141","DOI":"10.1109\/DATE.2002.998261"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06261-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11227-024-06261-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06261-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,2]],"date-time":"2024-08-02T13:49:27Z","timestamp":1722606567000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11227-024-06261-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,1]]},"references-count":26,"journal-issue":{"issue":"14","published-print":{"date-parts":[[2024,9]]}},"alternative-id":["6261"],"URL":"https:\/\/doi.org\/10.1007\/s11227-024-06261-z","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,6,1]]},"assertion":[{"value":"21 May 2024","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 June 2024","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}