{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,19]],"date-time":"2026-05-19T14:59:49Z","timestamp":1779202789799,"version":"3.51.4"},"reference-count":19,"publisher":"Springer Science and Business Media LLC","issue":"16","license":[{"start":{"date-parts":[[2024,7,23]],"date-time":"2024-07-23T00:00:00Z","timestamp":1721692800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,7,23]],"date-time":"2024-07-23T00:00:00Z","timestamp":1721692800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2024,11]]},"DOI":"10.1007\/s11227-024-06370-9","type":"journal-article","created":{"date-parts":[[2024,7,23]],"date-time":"2024-07-23T17:03:48Z","timestamp":1721754228000},"page":"23794-23814","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["A mini I2C bus interface circuit design and its VLSI implementation"],"prefix":"10.1007","volume":"80","author":[{"given":"Caixia","family":"Huang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sen","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,7,23]]},"reference":[{"key":"6370_CR1","unstructured":"I2C Bus Specification (2000) Philips Semiconductor, version 2.1"},{"issue":"3","key":"6370_CR2","first-page":"4","volume":"32","author":"C An","year":"2002","unstructured":"An C, Changwen T, Hao M (2002) Design of mini I2C bus interface circuit and its VLSI implementation. Microelectronics 32(3):4","journal-title":"Microelectronics"},{"key":"6370_CR3","doi-asserted-by":"crossref","unstructured":"Andrysiewicz W, Ko\u015bcielnik D, Mi\u015bkowicz M (2015) I2C hardware master serial interface for asynchronous ADCs. In: IEEE International Symposium on Systems Engineering (ISSE), Rome, Italy, pp. 77-81","DOI":"10.1109\/SysEng.2015.7302736"},{"key":"6370_CR4","doi-asserted-by":"crossref","unstructured":"Liu C, Meng Q, Liao T, Bao X, Xu C (2019) A Flexible Hardware Architecture for Slave Device of I2C Bus. In: 2019 International Conference on Electronic Engineering and Informatics (EEI), Nanjing, China, pp. 309\u2013313.","DOI":"10.1109\/EEI48997.2019.00074"},{"key":"6370_CR5","doi-asserted-by":"crossref","unstructured":"Deepika D, Yadav N (2018) Design of Dual Master I2C Bus Controller and Interfacing it With DC Motor. In: 2018 International Conference on Advances in Computing, Communication Control and Networking (ICACCCN), Greater Noida, India, pp. 668\u2013673.","DOI":"10.1109\/ICACCCN.2018.8748677"},{"key":"6370_CR6","doi-asserted-by":"crossref","unstructured":"Hu ZW (2010) I2C Protocol Design for Reusability. In: 2010 Third International Symposium on Information Processing, Qingdao, China, pp. 83-86","DOI":"10.1109\/ISIP.2010.51"},{"key":"6370_CR7","first-page":"331","volume":"11","author":"R Gupta","year":"2019","unstructured":"Gupta R, Kumar A, Sahay G (2019) Design and implementation of I2C interface on FPGA for space borne AIS receiver in embedded system. Int J Inf Technol 11:331\u2013340","journal-title":"Int J Inf Technol"},{"issue":"1","key":"6370_CR8","doi-asserted-by":"publisher","first-page":"30","DOI":"10.7454\/mst.v26i1.1416","volume":"26","author":"MK Ishak","year":"2022","unstructured":"Ishak MK, Kumar MP (2022) Design and implementation of I2C bus protocol on master and slave data transfer based on FPGA. Makara J Technol. 26(1):30\u201336","journal-title":"Makara J Technol."},{"key":"6370_CR9","doi-asserted-by":"crossref","unstructured":"Li L, Wang Y, Chen X, Ren X (2023) Research on Improvement of Configurable I2C Controller IP Core. In: 2023 IEEE International Conference on Control, Electronics and Computer Technology (ICCECT), Jilin, China","DOI":"10.1109\/ICCECT57938.2023.10141414"},{"issue":"1","key":"6370_CR10","doi-asserted-by":"publisher","first-page":"19","DOI":"10.15406\/oajs.2023.06.00188","volume":"6","author":"JCM Gonzalez","year":"2023","unstructured":"Gonzalez JCM (2023) Implementation of I2C and SPI communication protocol for temperature and acceleration measurement at FPGA. Open Access J Sci 6(1):19\u201322","journal-title":"Open Access J Sci"},{"key":"6370_CR11","unstructured":"ShenZhen BJX (2019) Microelectronics Technology CO.BJ8M306A, Datasheet.2019.12.2."},{"key":"6370_CR12","unstructured":"GigaDevice Semiconductor Inc. (2022) GD32F1x0, Datasheet"},{"key":"6370_CR13","unstructured":"Forencich A (n.d.). verilog-i2c. GitHub repository. Retrieved from https:\/\/github.com\/alexforencich\/verilog-i2c"},{"issue":"08","key":"6370_CR14","doi-asserted-by":"publisher","first-page":"5","DOI":"10.19339\/j.issn.1674-2583.2020.08.002","volume":"37","author":"Li Qinglong","year":"2020","unstructured":"Qinglong Li, Pan W, Libo T (2020) Design of integrated circuit I2C module master-slave mode and boot control. Integr Circuit Appl 37(08):5\u20138. https:\/\/doi.org\/10.19339\/j.issn.1674-2583.2020.08.002","journal-title":"Integr Circuit Appl"},{"issue":"03","key":"6370_CR15","doi-asserted-by":"publisher","first-page":"195","DOI":"10.16453\/j.issn.2095-8595.2016.03.001","volume":"03","author":"C Xinglong","year":"2016","unstructured":"Xinglong C, Hai T, Peng R, Jian Li (2016) Design and application of I2C bus based on FPGA. Electr Sci Technol 03(03):195\u2013199. https:\/\/doi.org\/10.16453\/j.issn.2095-8595.2016.03.001","journal-title":"Electr Sci Technol"},{"issue":"4","key":"6370_CR16","doi-asserted-by":"publisher","first-page":"611","DOI":"10.1142\/S021812660800454X","volume":"17","author":"AK Oudjida","year":"2008","unstructured":"Oudjida AK et al (2008) Universal low\/medium speed I2C slave transceiver: a detailed FPGA implementation. J Circuits Syst Comput 17(4):611\u2013626","journal-title":"J Circuits Syst Comput"},{"key":"6370_CR17","first-page":"678","volume":"2","author":"E Bollam","year":"2015","unstructured":"Bollam E, Ponmagal N, Preethi K, Sreejeesh SG (2015) Implementation of I2C master bus controller on FPGA. Int J Curr Eng Sci Res 2:678\u2013681","journal-title":"Int J Curr Eng Sci Res"},{"key":"6370_CR18","doi-asserted-by":"publisher","first-page":"51","DOI":"10.5121\/vlsic.2015.6405","volume":"6","author":"S Sindhu","year":"2015","unstructured":"Sindhu S, Vijaya Prakash AM, Ankit KV (2015) ASIC implementation of I2C master bus controller firm IP core. Int J VLSI Des Commun Sys 6:51\u201363","journal-title":"Int J VLSI Des Commun Sys"},{"key":"6370_CR19","unstructured":"Philips Semiconductors (1988) The I2C-bus specification, version 2.0, pp 2\u201340"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06370-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11227-024-06370-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06370-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,24]],"date-time":"2024-08-24T12:19:40Z","timestamp":1724501980000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11227-024-06370-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,23]]},"references-count":19,"journal-issue":{"issue":"16","published-print":{"date-parts":[[2024,11]]}},"alternative-id":["6370"],"URL":"https:\/\/doi.org\/10.1007\/s11227-024-06370-9","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,7,23]]},"assertion":[{"value":"16 July 2024","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"23 July 2024","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}