{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,1,20]],"date-time":"2026-01-20T12:58:45Z","timestamp":1768913925660,"version":"3.49.0"},"reference-count":43,"publisher":"Springer Science and Business Media LLC","issue":"16","license":[{"start":{"date-parts":[[2024,7,26]],"date-time":"2024-07-26T00:00:00Z","timestamp":1721952000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2024,7,26]],"date-time":"2024-07-26T00:00:00Z","timestamp":1721952000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"published-print":{"date-parts":[[2024,11]]},"DOI":"10.1007\/s11227-024-06371-8","type":"journal-article","created":{"date-parts":[[2024,7,27]],"date-time":"2024-07-27T00:02:04Z","timestamp":1722038524000},"page":"24689-24717","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":5,"title":["Adaptive PUF design to authenticate and evaluate heterogeneous IPs in edge computing"],"prefix":"10.1007","volume":"80","author":[{"given":"S.","family":"Hemavathy","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Kokila","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"V. S.","family":"Kanchana Bhaaskaran","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,7,26]]},"reference":[{"key":"6371_CR1","doi-asserted-by":"crossref","unstructured":"Majzoobi M, Koushanfar F, Potkonjak M, Tehranipoor M, Wang C (2012) FPGA oriented Security. Introduction to hardware security and trust, pp 195\u2013231","DOI":"10.1007\/978-1-4419-8080-9_9"},{"key":"6371_CR2","doi-asserted-by":"crossref","unstructured":"Guajardo J, Kumar S.S, Schrijen G.-J, Tuyls P (2007). FPGA intrinsic PUFs and their use for IP protection. In: Cryptographic Hardware and Embedded Systems-CHES 2007: 9th International Workshop, Vienna, Austria, September 10-13, 2007. Proceedings 9, pp 63\u201380 . Springer","DOI":"10.1007\/978-3-540-74735-2_5"},{"key":"6371_CR3","doi-asserted-by":"publisher","unstructured":"Chang C.-H, Potkonjak M (2016). Secure system design and trustable computing. Springer, Switzerland . https:\/\/doi.org\/10.1007\/978-3-319-14971-4","DOI":"10.1007\/978-3-319-14971-4"},{"key":"6371_CR4","doi-asserted-by":"publisher","first-page":"543","DOI":"10.1007\/s10836-019-05808-w","volume":"35","author":"J Kokila","year":"2019","unstructured":"Kokila J, Ramasubramanian N (2019) Enhanced authentication using hybrid PUF with FSM for protecting IPs of SoC FPGAs. J Electron Test 35:543\u2013558. https:\/\/doi.org\/10.1007\/s10836-019-05808-w","journal-title":"J Electron Test"},{"issue":"10","key":"6371_CR5","doi-asserted-by":"publisher","first-page":"2284","DOI":"10.1109\/TVLSI.2019.2926788","volume":"27","author":"J Kokila","year":"2019","unstructured":"Kokila J, Ramasubramanian N, Naganathan N (2019) Resource efficient metering scheme for protecting SoC FPGA device and IPs in IoT applications. IEEE Trans Very Large Scale Integr Syst 27(10):2284\u20132295. https:\/\/doi.org\/10.1109\/TVLSI.2019.2926788","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"6371_CR6","doi-asserted-by":"publisher","unstructured":"Zhang J, Wu Q, Lyu Y, Zhou Q, Cai Y, Lin Y, Qu G (2013) Design and implementation of a delay-based PUF for FPGA IP Protection. In: 2013 International Conference on Computer-Aided Design and Computer Graphics, pp 107\u2013114 . https:\/\/doi.org\/10.1109\/CADGraphics.2013.22","DOI":"10.1109\/CADGraphics.2013.22"},{"key":"6371_CR7","unstructured":"Anandakumar NN, Rahman MS, Rahman MMM, Kibria R, Das U, Farahmandi F, Rahman F, Tehranipoor MM (2022) Rethinking watermark: Providing proof of IP ownership in modern SoCs. Cryptology ePrint Archive"},{"key":"6371_CR8","unstructured":"Inc X. Using Encryption and Authentication to Secure an UltraScale\/UltraScale+ FPGA Bitstream Application Note (XAPP1267). https:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1267-encryp-efuse-program.pdf"},{"key":"6371_CR9","unstructured":"Inc X. Developing Tamper-Resistant Designs with Zynq UltraScale+ Devices. https:\/\/www.xilinx.com\/support\/documentation\/application_notes\/xapp1323-zynq-usp-tamper-resistant-designs.pdf"},{"issue":"2","key":"6371_CR10","doi-asserted-by":"publisher","first-page":"364","DOI":"10.1109\/TVLSI.2018.2877438","volume":"27","author":"MA Usmani","year":"2019","unstructured":"Usmani MA, Keshavarz S, Matthews E, Shannon L, Tessier R, Holcomb DE (2019) Efficient PUF-based key generation in FPGAs using per-device configuration. IEEE Trans Very Large Scale Integr Syst 27(2):364\u2013375. https:\/\/doi.org\/10.1109\/TVLSI.2018.2877438","journal-title":"IEEE Trans Very Large Scale Integr Syst"},{"key":"6371_CR11","doi-asserted-by":"publisher","DOI":"10.3390\/s19143208","author":"A Babaei","year":"2019","unstructured":"Babaei A, Schiele G (2019) Physical unclonable functions in the internet of things: state of the art and open challenges. Sensors. https:\/\/doi.org\/10.3390\/s19143208","journal-title":"Sensors"},{"issue":"1","key":"6371_CR12","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/CADGraphics.2013.22","volume":"2020","author":"A Balan","year":"2020","unstructured":"Balan A, Balan T, Cirstea M, Sandu F (2020) A PUF-based cryptographic security solution for IoT systems on chip. EURASIP J Wirel Commun Netw 2020(1):1\u201322. https:\/\/doi.org\/10.1109\/CADGraphics.2013.22","journal-title":"EURASIP J Wirel Commun Netw"},{"issue":"6","key":"6371_CR13","doi-asserted-by":"publisher","first-page":"1137","DOI":"10.1109\/TIFS.2015.2400413","volume":"10","author":"J Zhang","year":"2015","unstructured":"Zhang J, Lin Y, Lyu Y, Qu G (2015) A PUF-FSM binding scheme for FPGA IP protection and pay-per-device licensing. IEEE Trans Inf Forensics Secur 10(6):1137\u20131150. https:\/\/doi.org\/10.1109\/TIFS.2015.2400413","journal-title":"IEEE Trans Inf Forensics Secur"},{"key":"6371_CR14","doi-asserted-by":"publisher","first-page":"33979","DOI":"10.1109\/ACCESS.2023.3264016","volume":"11","author":"S Hemavathy","year":"2023","unstructured":"Hemavathy S, Bhaaskaran VSK (2023) Arbiter puf-a review of design, composition, and security aspects. IEEE Access 11:33979\u201334004. https:\/\/doi.org\/10.1109\/ACCESS.2023.3264016","journal-title":"IEEE Access"},{"key":"6371_CR15","doi-asserted-by":"publisher","unstructured":"Gao M, Lai K, Qu G (2014). A highly flexible ring oscillator PUF. In: 2014 51st ACM\/EDAC\/IEEE Design Automation Conference (DAC), pp 1\u20136 . https:\/\/doi.org\/10.1145\/2593069.2593072","DOI":"10.1145\/2593069.2593072"},{"key":"6371_CR16","doi-asserted-by":"publisher","unstructured":"Cherif Z, Danger J.-L, Guilley S, Bossuet L (2012). An easy-to-design PUF based on a single oscillator: The loop puf. In: 2012 15th Euromicro Conference on Digital System Design, pp 156\u2013162. https:\/\/doi.org\/10.1109\/DSD.2012.22","DOI":"10.1109\/DSD.2012.22"},{"key":"6371_CR17","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-023-05450-6","author":"A Roy","year":"2023","unstructured":"Roy A, Kokila J, Ramasubramanian N, Begum BS (2023) Device-specific security challenges and solution in IoT edge computing: a review. J Supercomput. https:\/\/doi.org\/10.1007\/s11227-023-05450-6","journal-title":"J Supercomput"},{"key":"6371_CR18","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2020.113595","volume":"106","author":"S Khan","year":"2020","unstructured":"Khan S, Shah AP, Chouhan SS, Gupta N, Pandey JG, Vishvakarma SK (2020) A symmetric D flip-flop based PUF with improved uniqueness. Microelectron Reliab 106:113595. https:\/\/doi.org\/10.1016\/j.microrel.2020.113595","journal-title":"Microelectron Reliab"},{"key":"6371_CR19","doi-asserted-by":"publisher","DOI":"10.1145\/3588435","author":"Y Liu","year":"2023","unstructured":"Liu Y, Li J, Qu T, Dai Z (2023) CBDC-PUF: A novel physical unclonable function design framework utilizing configurable butterfly delay chain against modeling attack. ACM Trans Des Autom Electron Syst. https:\/\/doi.org\/10.1145\/3588435","journal-title":"ACM Trans Des Autom Electron Syst"},{"key":"6371_CR20","doi-asserted-by":"publisher","DOI":"10.1145\/3517813","author":"NN Anandakumar","year":"2022","unstructured":"Anandakumar NN, Hashmi MS, Sanadhya SK (2022) Design and analysis of fpga-based pufs with enhanced performance for hardware-oriented security. J Emerg Technol Comput Syst. https:\/\/doi.org\/10.1145\/3517813","journal-title":"J Emerg Technol Comput Syst"},{"issue":"3","key":"6371_CR21","doi-asserted-by":"publisher","first-page":"405","DOI":"10.1109\/TCAD.2020.2999907","volume":"40","author":"AS Shanta","year":"2021","unstructured":"Shanta AS, Majumder MB, Hasan MS, Rose GS (2021) Physically unclonable and reconfigurable computing system (purcs) for hardware security applications. IEEE Trans Comput Aided Des Integr Circuits Syst 40(3):405\u2013418. https:\/\/doi.org\/10.1109\/TCAD.2020.2999907","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"issue":"1","key":"6371_CR22","doi-asserted-by":"publisher","first-page":"98","DOI":"10.1109\/TIFS.2011.2169667","volume":"7","author":"R Maes","year":"2012","unstructured":"Maes R, Schellekens D, Verbauwhede I (2012) A pay-per-use licensing scheme for hardware ip cores in recent SRAM-based FPGAs. IEEE Trans Inf Forensics Secur 7(1):98\u2013108. https:\/\/doi.org\/10.1109\/TIFS.2011.2169667","journal-title":"IEEE Trans Inf Forensics Secur"},{"key":"6371_CR23","doi-asserted-by":"publisher","first-page":"124785","DOI":"10.1109\/ACCESS.2019.2925106","volume":"7","author":"J Long","year":"2019","unstructured":"Long J, Liang W, Li K-C, Zhang D, Tang M, Luo H (2019) PUF-based anonymous authentication scheme for hardware devices and IPs in edge computing environment. IEEE Access 7:124785\u2013124796. https:\/\/doi.org\/10.1109\/ACCESS.2019.2925106","journal-title":"IEEE Access"},{"issue":"11","key":"6371_CR24","doi-asserted-by":"publisher","first-page":"2624","DOI":"10.1109\/TIFS.2016.2553454","volume":"11","author":"L Bossuet","year":"2016","unstructured":"Bossuet L, Colombier B (2016) Comments onA PUF-FSM binding scheme for FPGA IP protection and pay-per-device licensing. IEEE Trans Inf Forensics Secur 11(11):2624\u20132625. https:\/\/doi.org\/10.1109\/TIFS.2016.2553454","journal-title":"IEEE Trans Inf Forensics Secur"},{"key":"6371_CR25","doi-asserted-by":"publisher","unstructured":"Sun P, Cui A (2019) A new pay-per-use scheme for the protection of FPGA IP. In: 2019 IEEE International Symposium on Circuits and Systems (ISCAS), pp 1\u20135. https:\/\/doi.org\/10.1109\/ISCAS.2019.8702721","DOI":"10.1109\/ISCAS.2019.8702721"},{"issue":"1","key":"6371_CR26","doi-asserted-by":"publisher","first-page":"51","DOI":"10.1109\/TIFS.2011.2163307","volume":"7","author":"F Koushanfar","year":"2012","unstructured":"Koushanfar F (2012) Provably secure active ic metering techniques for piracy avoidance and digital rights management. IEEE Trans Inf Forensics Secur 7(1):51\u201363. https:\/\/doi.org\/10.1109\/TIFS.2011.2163307","journal-title":"IEEE Trans Inf Forensics Secur"},{"key":"6371_CR27","doi-asserted-by":"publisher","unstructured":"Anderson JH (2010). A PUF design for secure FPGA-based embedded systems. In: 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC), pp 1\u20136. https:\/\/doi.org\/10.1109\/ASPDAC.2010.5419927","DOI":"10.1109\/ASPDAC.2010.5419927"},{"key":"6371_CR28","doi-asserted-by":"publisher","unstructured":"Ma Q, Gu C, Hanley N, Wang C, Liu W, O\u2019Neill M (2018) A machine learning attack resistant multi-PUF design on FPGA. In: 2018 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), pp 97\u2013104. https:\/\/doi.org\/10.1109\/ASPDAC.2018.8297289","DOI":"10.1109\/ASPDAC.2018.8297289"},{"key":"6371_CR29","doi-asserted-by":"publisher","DOI":"10.3390\/electronics9050815","author":"Y Cui","year":"2020","unstructured":"Cui Y, Gu C, Ma Q, Fang Y, Wang C, O\u2019Neill M, Liu W (2020) Lightweight modeling attack-resistant multiplexer-based multi-PUF (MMPUF) design on FPGA. Electronics. https:\/\/doi.org\/10.3390\/electronics9050815","journal-title":"Electronics"},{"key":"6371_CR30","unstructured":"Santikellur P, Bhattacharyay A, Chakraborty RS (2019) Deep learning based model building attacks on arbiter PUF compositions. Cryptology ePrint Archive"},{"key":"6371_CR31","doi-asserted-by":"publisher","DOI":"10.3390\/app11209730","author":"Z Zulfikar","year":"2021","unstructured":"Zulfikar Z, Soin N, Wan Muhamad Hatta SF, Abu Talip MS, Jaafar A (2021) Routing density analysis of area-efficient ring oscillator physically unclonable functions. Appl Sci. https:\/\/doi.org\/10.3390\/app11209730","journal-title":"Appl Sci"},{"key":"6371_CR32","doi-asserted-by":"publisher","first-page":"64778","DOI":"10.1109\/ACCESS.2019.2917259","volume":"7","author":"S Hou","year":"2019","unstructured":"Hou S, Guo Y, Li S (2019) A lightweight LFSR-based strong physical unclonable function design on FPGA. IEEE Access 7:64778\u201364787. https:\/\/doi.org\/10.1109\/ACCESS.2019.2917259","journal-title":"IEEE Access"},{"key":"6371_CR33","doi-asserted-by":"crossref","unstructured":"Maiti A, Gunreddy V, Schaumont P (2013) A systematic method to evaluate and compare the performance of physical unclonable functions. Embedded systems design with FPGAs, pp 245\u2013267","DOI":"10.1007\/978-1-4614-1362-2_11"},{"key":"6371_CR34","doi-asserted-by":"publisher","unstructured":"Sahoo DP, Saha S, Mukhopadhyay D, Chakraborty RS, Kapoor H (2014) Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA. In: 2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST), pp 50\u201355. https:\/\/doi.org\/10.1109\/HST.2014.6855567","DOI":"10.1109\/HST.2014.6855567"},{"key":"6371_CR35","doi-asserted-by":"publisher","unstructured":"Sankaran S, Shivshankar S, Nimmy K (2018) LHPUF: lightweight hybrid PUF for enhanced security in internet of things. In: 2018 IEEE International Symposium on Smart Electronic Systems (iSES) (Formerly iNiS), pp 275\u2013278. https:\/\/doi.org\/10.1109\/iSES.2018.00066","DOI":"10.1109\/iSES.2018.00066"},{"key":"6371_CR36","doi-asserted-by":"publisher","DOI":"10.1016\/j.micpro.2020.103180","volume":"77","author":"NN Anandakumar","year":"2020","unstructured":"Anandakumar NN, Hashmi MS, Sanadhya SK (2020) Efficient and lightweight FPGA-based Hybrid PUFs with improved performance. Microprocess Microsyst 77:103180. https:\/\/doi.org\/10.1016\/j.micpro.2020.103180","journal-title":"Microprocess Microsyst"},{"issue":"7","key":"6371_CR37","doi-asserted-by":"publisher","first-page":"1143","DOI":"10.1109\/TCAD.2015.2424955","volume":"34","author":"Y Cao","year":"2015","unstructured":"Cao Y, Zhang L, Chang C-H, Chen S (2015) A low-power hybrid RO PUF with improved thermal stability for lightweight applications. IEEE Trans Comput Aided Des Integr Circuits Syst 34(7):1143\u20131147. https:\/\/doi.org\/10.1109\/TCAD.2015.2424955","journal-title":"IEEE Trans Comput Aided Des Integr Circuits Syst"},{"key":"6371_CR38","unstructured":"Khoshroo S (2013) Design and Evaluation of FPGA-based Hybrid Physically Unclonable Functions. PhD thesis, Western University . Electronic Thesis and Dissertation Repository. 1281"},{"issue":"7","key":"6371_CR39","doi-asserted-by":"publisher","first-page":"827","DOI":"10.1109\/TCSII.2016.2602828","volume":"64","author":"T Tanamoto","year":"2017","unstructured":"Tanamoto T, Yasuda S, Takaya S, Fujita S (2017) Physically unclonable function using an initial waveform of ring oscillators. IEEE Trans Circuits Syst II Express Briefs 64(7):827\u2013831. https:\/\/doi.org\/10.1109\/TCSII.2016.2602828","journal-title":"IEEE Trans Circuits Syst II Express Briefs"},{"key":"6371_CR40","doi-asserted-by":"publisher","unstructured":"Zheng Y, Huang Z, Li L, Xie C, Wang Q, Wu Z (2021) Implementation and analysis of Hybrid DRAM PUFs on FPGA. In: 2021 International Conference on Networking and Network Applications (NaNA), pp 390\u2013394. https:\/\/doi.org\/10.1109\/NaNA53684.2021.00074","DOI":"10.1109\/NaNA53684.2021.00074"},{"key":"6371_CR41","doi-asserted-by":"publisher","unstructured":"Stolz F, Albartus N, Speith J, Klix S, Nasenberg C, Gula A, Fyrbiak M, Paar C, G\u00fcneysu T, Tessier R (2021) LifeLine for FPGA protection: obfuscated cryptography for real-world security. Cryptology ePrint Archive, Paper 2021\/1277. https:\/\/doi.org\/10.46586\/tches.v2021.i4.412-446 . https:\/\/eprint.iacr.org\/2021\/1277","DOI":"10.46586\/tches.v2021.i4.412-446"},{"key":"6371_CR42","doi-asserted-by":"publisher","DOI":"10.1145\/3609388","author":"H Nassar","year":"2023","unstructured":"Nassar H, Bauer L, Henkel J (2023) ANV-PUF: machine-learning-resilient NVM-based arbiter PUF. ACM Trans Embed Comput Syst. https:\/\/doi.org\/10.1145\/3609388","journal-title":"ACM Trans Embed Comput Syst"},{"key":"6371_CR43","doi-asserted-by":"publisher","DOI":"10.1016\/j.mejo.2023.105977","volume":"142","author":"X Ma","year":"2023","unstructured":"Ma X, Wang P, Li G, Zhou Z (2023) Machine learning attacks resistant strong PUF design utilizing response obfuscates challenge with lower hardware overhead. Microelectron J 142:105977. https:\/\/doi.org\/10.1016\/j.mejo.2023.105977","journal-title":"Microelectron J"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06371-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11227-024-06371-8\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-024-06371-8.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,22]],"date-time":"2024-08-22T17:01:48Z","timestamp":1724346108000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11227-024-06371-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,7,26]]},"references-count":43,"journal-issue":{"issue":"16","published-print":{"date-parts":[[2024,11]]}},"alternative-id":["6371"],"URL":"https:\/\/doi.org\/10.1007\/s11227-024-06371-8","relation":{},"ISSN":["0920-8542","1573-0484"],"issn-type":[{"value":"0920-8542","type":"print"},{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,7,26]]},"assertion":[{"value":"16 July 2024","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 July 2024","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors whose names are listed certify that they have no affiliations with or involvement in any organization or entity with any financial interest (such as honoraria, educational grants, participation in speakers\u2019bureaus, membership, employment, consultancies, stock ownership, or other equity interest and expert testimony or patent-licensing arrangements), or nonfinancial interest (such as personal or professional relationships, affiliations, knowledge, or beliefs) in the subject matter or materials discussed in this manuscript.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}]}}