{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T17:30:21Z","timestamp":1764351021993,"version":"3.46.0"},"reference-count":90,"publisher":"Springer Science and Business Media LLC","issue":"17","license":[{"start":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T00:00:00Z","timestamp":1764288000000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"},{"start":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T00:00:00Z","timestamp":1764288000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/www.springernature.com\/gp\/researchers\/text-and-data-mining"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204"],"award-info":[{"award-number":["Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204","Grant U21B2030, Grant U24B6015 and Grant 92264204"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Supercomput"],"DOI":"10.1007\/s11227-025-08080-2","type":"journal-article","created":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T17:24:13Z","timestamp":1764350653000},"update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["ROM-SRAM hybrid compute-in-memory for edge AI: circuits, architectures and challenges"],"prefix":"10.1007","volume":"81","author":[{"given":"Xirui","family":"Du","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianyi","family":"Yu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hengping","family":"Zhou","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ling-An","family":"Cheong","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Teng","family":"Wan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Xueqing","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2025,11,28]]},"reference":[{"key":"8080_CR1","doi-asserted-by":"publisher","unstructured":"He K, Zhang X, Ren S, Sun J (2016) Deep residual learning for image recognition. In: 2016 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 770\u2013778. https:\/\/doi.org\/10.1109\/CVPR.2016.90","DOI":"10.1109\/CVPR.2016.90"},{"key":"8080_CR2","unstructured":"Blattmann A, Dockhorn T, Kulal S, Mendelevitch D, Kilian M, Lorenz D, Levi Y, English Z, Voleti V, Letts A, Jampani V, Rombach R (2023) Stable video diffusion: scaling latent video diffusion models to large datasets. https:\/\/arxiv.org\/abs\/2311.15127"},{"key":"8080_CR3","unstructured":"Touvron H, Lavril T, Izacard G, Martinet X, Lachaux M-A, Lacroix T, Rozi\u00e8re B, Goyal N, Hambro E, Azhar F, Rodriguez A, Joulin A, Grave E, Lample G (2023) LLaMA: open and efficient foundation language models. https:\/\/arxiv.org\/abs\/2302.13971"},{"issue":"6","key":"8080_CR4","doi-asserted-by":"publisher","first-page":"84","DOI":"10.1145\/3065386","volume":"60","author":"A Krizhevsky","year":"2017","unstructured":"Krizhevsky A, Sutskever I, Hinton GE (2017) Imagenet classification with deep convolutional neural networks. Commun ACM 60(6):84\u201390. https:\/\/doi.org\/10.1145\/3065386","journal-title":"Commun ACM"},{"key":"8080_CR5","doi-asserted-by":"publisher","unstructured":"Yenduri G, Ramalingam M, Selvi GC, Supriya Y, Srivastava G, Maddikunta PKR, Raj GD, Jhaveri RH, Prabadevi B, Wang W, Vasilakos AV, Gadekallu TR (2024) pt (generative pre-trained transformer)\u2014 a comprehensive review on enabling technologies, potential applications, emerging challenges, and future directions. IEEE Access 12, 54608\u201354649 https:\/\/doi.org\/10.1109\/ACCESS.2024.3389497","DOI":"10.1109\/ACCESS.2024.3389497"},{"key":"8080_CR6","unstructured":"Zhang S, Roller S, Goyal N, Artetxe M, Chen M, Chen S, Dewan C, Diab M, Li X, Lin XV, Mihaylov T, Ott M, Shleifer S, Shuster K, Simig D, Koura PS, Sridhar A, Wang T, Zettlemoyer L (2022) OPT: open pre-trained transformer language models. https:\/\/arxiv.org\/abs\/2205.01068"},{"issue":"12","key":"8080_CR7","doi-asserted-by":"publisher","first-page":"4821","DOI":"10.1109\/TCSI.2021.3095622","volume":"68","author":"L Ye","year":"2021","unstructured":"Ye L, Wang Z, Liu Y, Chen P, Li H, Zhang H, Wu M, He W, Shen L, Zhang Y, Tan Z, Wang Y, Huang R (2021) The challenges and emerging technologies for low-power artificial intelligence iot systems. IEEE Trans Circuits Syst I Regul Pap 68(12):4821\u20134834. https:\/\/doi.org\/10.1109\/TCSI.2021.3095622","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"8080_CR8","unstructured":"Zhou S, Wu Y, Ni Z, Zhou X, Wen H, Zou Y (2018) DoReFa-Net: training low bitwidth convolutional neural networks with low bitwidth gradients. https:\/\/arxiv.org\/abs\/1606.06160"},{"key":"8080_CR9","doi-asserted-by":"crossref","unstructured":"Chen T, Bao H, Huang S, Dong L, Jiao B, Jiang D, Zhou H, Li J, Wei F (2022) THE-X: privacy-preserving transformer inference with homomorphic encryption. https:\/\/arxiv.org\/abs\/2206.00216","DOI":"10.18653\/v1\/2022.findings-acl.277"},{"key":"8080_CR10","doi-asserted-by":"publisher","unstructured":"Song J, Wang Y, Tang X, Wang R, Huang R (2021) A 16kb transpose 6t sram in-memory-computing macro based on robust charge-domain computing. In: 2021 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1\u20133 . https:\/\/doi.org\/10.1109\/A-SSCC53895.2021.9634747","DOI":"10.1109\/A-SSCC53895.2021.9634747"},{"issue":"1","key":"8080_CR11","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1145\/216585.216588","volume":"23","author":"WA Wulf","year":"1995","unstructured":"Wulf WA, McKee SA (1995) Hitting the memory wall: implications of the obvious. SIGARCH Comput Archit News 23(1):20\u201324. https:\/\/doi.org\/10.1145\/216585.216588","journal-title":"SIGARCH Comput Archit News"},{"key":"8080_CR12","doi-asserted-by":"publisher","unstructured":"Varghese R, M, S (2024) Yolov8: A novel object detection algorithm with enhanced performance and robustness. In: 2024 International Conference on Advances in Data Engineering and Intelligent Computing Systems (ADICS), 1\u20136. https:\/\/doi.org\/10.1109\/ADICS58448.2024.10533619","DOI":"10.1109\/ADICS58448.2024.10533619"},{"key":"8080_CR13","doi-asserted-by":"publisher","unstructured":"Devlin J, Chang M-W, Lee K, Toutanova K (2019) BERT: Pre-training of deep bidirectional transformers for language understanding. In: Burstein, J., Doran, C., Solorio, T. (eds.) Proceedings of the 2019 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies, Volume 1 (Long and Short Papers), 4171\u20134186. Association for Computational Linguistics, Minneapolis, Minnesota. https:\/\/doi.org\/10.18653\/v1\/N19-1423","DOI":"10.18653\/v1\/N19-1423"},{"key":"8080_CR14","unstructured":"Meta: Llama 3.2: Revolutionizing edge AI and vision with open, customizable models (2024). https:\/\/ai.meta.com\/blog\/llama-3-2-connect-2024-vision-edge-mobile-devices\/ Accessed 2025-09-24"},{"key":"8080_CR15","doi-asserted-by":"publisher","unstructured":"Kim J, Kim Y (2014) Hbm: Memory solution for bandwidth-hungry processors. In: 2014 IEEE Hot Chips 26 Symposium (HCS), 1\u201324 . https:\/\/doi.org\/10.1109\/HOTCHIPS.2014.7478812","DOI":"10.1109\/HOTCHIPS.2014.7478812"},{"key":"8080_CR16","doi-asserted-by":"publisher","unstructured":"Smith A, Loh GH, Wuu J, Naffziger S, Huang T, McIntyre H, Mangaser R, Jung W, Swaminathan R (2024) Amd instinct\u2122 mi300x accelerator: Packaging and architecture co-optimization. In: 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 1\u20132. https:\/\/doi.org\/10.1109\/VLSITechnologyandCir46783.2024.10631545","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631545"},{"issue":"7550","key":"8080_CR17","doi-asserted-by":"publisher","first-page":"61","DOI":"10.1038\/nature14441","volume":"521","author":"M Prezioso","year":"2015","unstructured":"Prezioso M, Merrikh-Bayat F, Hoskins BD, Adam GC, Likharev KK, Strukov DB (2015) Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 521(7550):61\u20134. https:\/\/doi.org\/10.1038\/nature14441","journal-title":"Nature"},{"key":"8080_CR18","doi-asserted-by":"publisher","unstructured":"Zhang J, Wang Z, Verma N (2016) A machine-learning classifier implemented in a standard 6t sram array. In: 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 1\u20132. https:\/\/doi.org\/10.1109\/VLSIC.2016.7573556","DOI":"10.1109\/VLSIC.2016.7573556"},{"issue":"12","key":"8080_CR19","doi-asserted-by":"publisher","first-page":"4219","DOI":"10.1109\/TCSI.2018.2848999","volume":"65","author":"A Agrawal","year":"2018","unstructured":"Agrawal A, Jaiswal A, Lee C, Roy K (2018) X-sram: enabling in-memory boolean computations in cmos static random access memories. IEEE Trans Circuits Syst I Regul Pap 65(12):4219\u20134232. https:\/\/doi.org\/10.1109\/TCSI.2018.2848999","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"issue":"1","key":"8080_CR20","doi-asserted-by":"publisher","first-page":"217","DOI":"10.1109\/JSSC.2018.2880918","volume":"54","author":"A Biswas","year":"2019","unstructured":"Biswas A, Chandrakasan AP (2019) Conv-sram: an energy-efficient sram with in-memory dot-product computation for low-power convolutional neural networks. IEEE J Solid-State Circuits 54(1):217\u2013230. https:\/\/doi.org\/10.1109\/JSSC.2018.2880918","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR21","doi-asserted-by":"publisher","unstructured":"Si X, Chen J-J, Tu Y-N, Huang W-H, Wang J-H, Chiu Y-C, Wei W-C, Wu S-Y, Sun X, Liu R, Yu S, Liu R-S, Hsieh C-C, Tang K-T, Li Q, Chang M-F (2019) 24.5 a twin-8t sram computation-in-memory macro for multiple-bit cnn-based machine learning. In: 2019 IEEE International Solid-State Circuits Conference - (ISSCC), 396\u2013398. https:\/\/doi.org\/10.1109\/ISSCC.2019.8662392","DOI":"10.1109\/ISSCC.2019.8662392"},{"key":"8080_CR22","doi-asserted-by":"publisher","unstructured":"Xie S, Ni C, Sayal A, Jain P, Hamzaoglu F, Kulkarni JP (2021) 16.2 edram-cim: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing. In: 2021 IEEE International Solid-State Circuits Conference (ISSCC), 64, 248\u2013250. https:\/\/doi.org\/10.1109\/ISSCC42613.2021.9365932","DOI":"10.1109\/ISSCC42613.2021.9365932"},{"key":"8080_CR23","doi-asserted-by":"publisher","unstructured":"Ha S, Kim S, Han D, Um S, Yoo H-J (2022) A 36.2 db high snr and pvt\/leakage-robust edram computing-in-memory macro with segmented bl and reference cell array. IEEE Trans Circuits Syst II: Express Briefs 69(5), 2433\u20132437 https:\/\/doi.org\/10.1109\/TCSII.2022.3159808","DOI":"10.1109\/TCSII.2022.3159808"},{"key":"8080_CR24","doi-asserted-by":"publisher","unstructured":"Khwa W-S, Wu P-C, Su J-W, Cheng C-Y, Hsu J-M, Chen Y-C, Hsieh L-J, Bai J-C, Kao Y-S, Lou T-H, Lele AS, Wu J-J, Tien J-C, Lo C-C, Liu R-S, Hsieh C-C, Tang K-T, Chang M-F (2025) 14.2 a 16nm 216kb, 188.4tops\/w and 133.5tflops\/w microscaling multi-mode gain-cell cim macro edge-ai devices. In: 2025 IEEE International Solid-State Circuits Conference (ISSCC), 68, 1\u20133. https:\/\/doi.org\/10.1109\/ISSCC49661.2025.10904606","DOI":"10.1109\/ISSCC49661.2025.10904606"},{"key":"8080_CR25","doi-asserted-by":"publisher","unstructured":"Gu P, Li B, Tang T, Yu S, Cao Y, Wang Y, Yang H (2015) Technological exploration of rram crossbar array for matrix-vector multiplication. In: The 20th Asia and South Pacific Design Automation Conference, 106\u2013111. https:\/\/doi.org\/10.1109\/ASPDAC.2015.7058989","DOI":"10.1109\/ASPDAC.2015.7058989"},{"issue":"11","key":"8080_CR26","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TMAG.2018.2848625","volume":"54","author":"Y Pan","year":"2018","unstructured":"Pan Y, Ouyang P, Zhao Y, Kang W, Yin S, Zhang Y, Zhao W, Wei S (2018) A multilevel cell stt-mram-based computing in-memory accelerator for binary convolutional neural network. IEEE Trans Magn 54(11):1\u20135. https:\/\/doi.org\/10.1109\/TMAG.2018.2848625","journal-title":"IEEE Trans Magn"},{"key":"8080_CR27","doi-asserted-by":"publisher","unstructured":"Cai H, Bian Z, Hou Y, Zhou Y, Cui J-l, Guo Y, Tian X, Liu B, Si X, Wang Z, Yang J, Shan W (2023) 33.4 a 28nm 2mb stt-mram computing-in-memory macro with a refined bit-cell and 22.4 - 41.5tops\/w for ai inference. In: 2023 IEEE International Solid-State Circuits Conference (ISSCC), 500\u2013502. https:\/\/doi.org\/10.1109\/ISSCC42615.2023.10067339","DOI":"10.1109\/ISSCC42615.2023.10067339"},{"key":"8080_CR28","doi-asserted-by":"publisher","unstructured":"Soliman T, M\u00fcller F, Kirchner T, Hoffmann T, Ganem H, Karimov E, Ali T, Lederer M, Sudarshan C, K\u00e4mpfe T, Guntoro A, Wehn N (2020) Ultra-low power flexible precision fefet based analog in-memory computing. In: 2020 IEEE International Electron Devices Meeting (IEDM), 29\u2013212924. https:\/\/doi.org\/10.1109\/IEDM13553.2020.9372124","DOI":"10.1109\/IEDM13553.2020.9372124"},{"key":"8080_CR29","doi-asserted-by":"publisher","unstructured":"Wang L, Li W, Zhou Z, Gao H, Li Z, Ye W, Hu H, Liu J, Yue J, Yang J, Luo Q, Dou C, Liu Q, Liu M (2024) 34.9 a flash-sram-adc-fused plastic computing-in-memory macro for learning in neural networks in a standard 14nm finfet process. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC), 67, 582\u2013584. https:\/\/doi.org\/10.1109\/ISSCC49657.2024.10454372","DOI":"10.1109\/ISSCC49657.2024.10454372"},{"issue":"5","key":"8080_CR30","doi-asserted-by":"publisher","first-page":"1773","DOI":"10.1109\/TCSI.2021.3064189","volume":"68","author":"C-J Jhang","year":"2021","unstructured":"Jhang C-J, Xue C-X, Hung J-M, Chang F-C, Chang M-F (2021) Challenges and trends of sram-based computing-in-memory for ai edge devices. IEEE Trans Circuits Syst I Regul Pap 68(5):1773\u20131786. https:\/\/doi.org\/10.1109\/TCSI.2021.3064189","journal-title":"IEEE Trans Circuits Syst I Regul Pap"},{"key":"8080_CR31","doi-asserted-by":"publisher","first-page":"171","DOI":"10.1109\/OJSSCS.2021.3123287","volume":"1","author":"J-M Hung","year":"2021","unstructured":"Hung J-M, Jhang C-J, Wu P-C, Chiu Y-C, Chang M-F (2021) Challenges and trends of nonvolatile in-memory-computation circuits for ai edge devices. IEEE Open J Solid-State Circuits Soc 1:171\u2013183. https:\/\/doi.org\/10.1109\/OJSSCS.2021.3123287","journal-title":"IEEE Open J Solid-State Circuits Soc"},{"key":"8080_CR32","doi-asserted-by":"publisher","unstructured":"Yan B, Hsu J-L, Yu P-C, Lee C-C, Zhang Y, Yue W, Mei G, Yang Y, Yang Y, Li H, Chen Y, Huang R (2022) A 1.041-mb\/mm2 27.38-tops\/w signed-int8 dynamic-logic-based adc-less sram compute-in-memory macro in 28nm with reconfigurable bitwise operation for ai and embedded applications. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), 65, 188\u2013190. https:\/\/doi.org\/10.1109\/ISSCC42614.2022.9731545","DOI":"10.1109\/ISSCC42614.2022.9731545"},{"issue":"6","key":"8080_CR33","doi-asserted-by":"publisher","first-page":"1789","DOI":"10.1109\/JSSC.2019.2899730","volume":"54","author":"H Valavi","year":"2019","unstructured":"Valavi H, Ramadge PJ, Nestler E, Verma N (2019) A 64-tile 2.4-mb in-memory-computing cnn accelerator employing charge-domain compute. IEEE J Solid-State Circuits 54(6):1789\u20131799. https:\/\/doi.org\/10.1109\/JSSC.2019.2899730","journal-title":"IEEE J Solid-State Circuits"},{"issue":"6","key":"8080_CR34","doi-asserted-by":"publisher","first-page":"1798","DOI":"10.1109\/JSSC.2022.3213542","volume":"58","author":"F Tu","year":"2023","unstructured":"Tu F, Wu Z, Wang Y, Liang L, Liu L, Ding Y, Liu L, Wei S, Xie Y, Yin S (2023) Trancim: full-digital bitline-transpose cim-based sparse transformer accelerator with pipeline\/parallel reconfigurable modes. IEEE J Solid-State Circuits 58(6):1798\u20131809. https:\/\/doi.org\/10.1109\/JSSC.2022.3213542","journal-title":"IEEE J Solid-State Circuits"},{"issue":"1","key":"8080_CR35","doi-asserted-by":"publisher","first-page":"90","DOI":"10.1109\/JSSC.2023.3305663","volume":"59","author":"F Tu","year":"2024","unstructured":"Tu F, Wu Z, Wang Y, Wu W, Liu L, Hu Y, Wei S, Yin S (2024) Multcim: digital computing-in-memory-based multimodal transformer accelerator with attention-token-bit hybrid sparsity. IEEE J Solid-State Circuits 59(1):90\u2013101. https:\/\/doi.org\/10.1109\/JSSC.2023.3305663","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR36","doi-asserted-by":"publisher","unstructured":"Wu Z, Wang Y, He Z, Yang B, Wang Y, Wei S, Hu Y, Tu F, Yin S (2025) Cella: A 28nm compute-memory co-optimized real-time digital cim-based edge llm accelerator with 1.78ms-response in prefill and 31.32 token\/s in decoding. In: 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 1\u20133 . https:\/\/doi.org\/10.23919\/VLSITechnologyandCir65189.2025.11075101","DOI":"10.23919\/VLSITechnologyandCir65189.2025.11075101"},{"issue":"10","key":"8080_CR37","doi-asserted-by":"publisher","first-page":"1379","DOI":"10.1109\/LED.2017.2748992","volume":"38","author":"K Chatterjee","year":"2017","unstructured":"Chatterjee K, Kim S, Karbasian G, Tan AJ, Yadav AK, Khan AI, Hu C, Salahuddin S (2017) Self-aligned, gate last, fdsoi, ferroelectric gate memory device with 5.5-nm hf0.8zr0.2o2, high endurance and breakdown recovery. IEEE Electron Dev Lett 38(10):1379\u20131382. https:\/\/doi.org\/10.1109\/LED.2017.2748992","journal-title":"IEEE Electron Dev Lett"},{"key":"8080_CR38","unstructured":"Hu EJ, Shen Y, Wallis P, Allen-Zhu Z, Li Y, Wang S, Wang L, Chen W (2021) LoRA: low-rank adaptation of large language models. https:\/\/arxiv.org\/abs\/2106.09685"},{"issue":"5786","key":"8080_CR39","doi-asserted-by":"publisher","first-page":"504","DOI":"10.1126\/science.1127647","volume":"313","author":"GE Hinton","year":"2006","unstructured":"Hinton GE, Salakhutdinov RR (2006) Reducing the dimensionality of data with neural networks. Science 313(5786):504\u2013507. https:\/\/doi.org\/10.1126\/science.1127647. (Publisher: American Association for the Advancement of Science (AAAS))","journal-title":"Science"},{"key":"8080_CR40","unstructured":"Vaswani A, Shazeer N, Parmar N, Uszkoreit J, Jones L, Gomez AN, Kaiser L, Polosukhin I (2023) attention is all you need. https:\/\/arxiv.org\/abs\/1706.03762"},{"key":"8080_CR41","unstructured":"Yosinski J, Clune J, Bengio Y, Lipson H (2014) How transferable are features in deep neural networks?"},{"key":"8080_CR42","doi-asserted-by":"publisher","unstructured":"Kang M, Keel M-S, Shanbhag NR, Eilert S, Curewitz K (2014) An energy-efficient vlsi architecture for pattern recognition via deep embedding of computation in sram. In: 2014 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), 8326\u20138330. https:\/\/doi.org\/10.1109\/ICASSP.2014.6855225","DOI":"10.1109\/ICASSP.2014.6855225"},{"issue":"1","key":"8080_CR43","doi-asserted-by":"publisher","first-page":"189","DOI":"10.1109\/JSSC.2019.2952773","volume":"55","author":"X Si","year":"2020","unstructured":"Si X, Chen J-J, Tu Y-N, Huang W-H, Wang J-H, Chiu Y-C, Wei W-C, Wu S-Y, Sun X, Liu R, Yu S, Liu R-S, Hsieh C-C, Tang K-T, Li Q, Chang M-F (2020) A twin-8t sram computation-in-memory unit-macro for multibit cnn-based ai edge processors. IEEE J Solid-State Circuits 55(1):189\u2013202. https:\/\/doi.org\/10.1109\/JSSC.2019.2952773","journal-title":"IEEE J Solid-State Circuits"},{"issue":"7","key":"8080_CR44","doi-asserted-by":"publisher","first-page":"1888","DOI":"10.1109\/JSSC.2020.2992886","volume":"55","author":"Z Jiang","year":"2020","unstructured":"Jiang Z, Yin S, Seo J-S, Seok M (2020) C3sram: an in-memory-computing sram macro based on robust capacitive coupling computing mechanism. IEEE J Solid-State Circuits 55(7):1888\u20131897. https:\/\/doi.org\/10.1109\/JSSC.2020.2992886","journal-title":"IEEE J Solid-State Circuits"},{"issue":"1","key":"8080_CR45","doi-asserted-by":"publisher","first-page":"308","DOI":"10.1109\/JSSC.2024.3422826","volume":"60","author":"Z Chen","year":"2025","unstructured":"Chen Z, Wen Z, Wan W, Reddy Pakala A, Zou Y, Wei W-C, Li Z, Chen Y, Yang K (2025) Pico-ram: a pvt-insensitive analog compute-in-memory sram macro with in situ multi-bit charge computing and 6t thin-cell-compatible layout. IEEE J Solid-State Circuits 60(1):308\u2013320. https:\/\/doi.org\/10.1109\/JSSC.2024.3422826","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR46","doi-asserted-by":"publisher","unstructured":"Yang J, Kong Y, Wang Z, Liu Y, Wang B, Yin S, Shi L (2019) 24.4 sandwich-ram: An energy-efficient in-memory bwn architecture with pulse-width modulation. In: 2019 IEEE International Solid-State Circuits Conference - (ISSCC), 394\u2013396. https:\/\/doi.org\/10.1109\/ISSCC.2019.8662435","DOI":"10.1109\/ISSCC.2019.8662435"},{"key":"8080_CR47","doi-asserted-by":"publisher","unstructured":"Wu P-C, Su J-W, Chung Y-L, Hong L-Y, Ren J-S, Chang F-C, Wu Y, Chen H-Y, Lin C-H, Hsiao H-M, Li S-H, Sheu S-S, Chang S-C, Lo W-C, Lo C-C, Liu R-S, Hsieh C-C, Tang K-T, Wu C-I, Chang M-F (2022) A 28nm 1mb time-domain computing-in-memory 6t-sram macro with a 6.6ns latency, 1241gops and 37.01tops\/w for 8b-mac operations for edge-ai devices. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), 65, 1\u20133. https:\/\/doi.org\/10.1109\/ISSCC42614.2022.9731681","DOI":"10.1109\/ISSCC42614.2022.9731681"},{"key":"8080_CR48","doi-asserted-by":"publisher","unstructured":"Chih Y-D, Lee P-H, Fujiwara H, Shih Y-C, Lee C-F, Naous R, Chen Y-L, Lo C-P, Lu C-H, Mori H, Zhao W-C, Sun D, Sinangil ME, Chen Y-H, Chou T-L, Akarvardar K, Liao H-J, Wang Y, Chang M-F, Chang T-YJ (2021) 16.4 an 89tops\/w and 16.3tops\/mm2 all-digital sram-based full-precision compute-in memory macro in 22nm for machine-learning edge applications. In: 2021 IEEE International Solid-State Circuits Conference (ISSCC), 64, 252\u2013254. https:\/\/doi.org\/10.1109\/ISSCC42613.2021.9365766","DOI":"10.1109\/ISSCC42613.2021.9365766"},{"key":"8080_CR49","doi-asserted-by":"publisher","unstructured":"Fujiwara H, Mori H, Zhao W-C, Khare K, Lee C-E, Peng X, Joshi V, Chuang C-K, Hsu S-H, Hashizume T, Naganuma T, Tien C-H, Liu Y-Y, Lai Y-C, Lee C-F, Chou T-L, Akarvardar K, Adham S, Wang Y, Chih Y-D,Chen Y-H, Liao H-J, Chang T-YJ (2024) 34.4 a 3nm, 32.5tops\/w, 55.0tops\/mm2 and 3.78mb\/mm2 fully-digital compute-in-memory macro supporting int12 $$\\times$$ int12 with a parallel-mac architecture and foundry 6t-sram bit cell. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC), 67,572\u2013574 . https:\/\/doi.org\/10.1109\/ISSCC49657.2024.10454556","DOI":"10.1109\/ISSCC49657.2024.10454556"},{"key":"8080_CR50","doi-asserted-by":"publisher","unstructured":"Yuan Y, Yang Y, Wang X, Li X, Ma C, Chen Q, Tang M, Wei X, Hou Z, Zhu J, Wu H, Ren Q, Xing G, Mak P-I, Zhang F (2024) 34.6 a 28nm 72.12tflops\/w hybrid-domain outer-product based floating-point sram computing-in-memory macro with logarithm bit-width residual adc. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC), 67, 576\u2013578. https:\/\/doi.org\/10.1109\/ISSCC49657.2024.10454313","DOI":"10.1109\/ISSCC49657.2024.10454313"},{"key":"8080_CR51","doi-asserted-by":"publisher","unstructured":"Chen X, Li S, Zhang Z, Zheng W, Tan X, Tang Y, Shi Y, Ren L, Mai Y, Liu F, Chen J, Zhang Z, Guo A, Xiong T, Wang B, Liu X, Shan W, Liu B, Cai H, Yang J, Si X (2025) 14.6 a 28nm 64kb bit-rotated hybrid-cim macro with an embedded sign-bit-processing array and a multi-bit-fusion dual-granularity cooperative quantizer. In: 2025 IEEE International Solid-State Circuits Conference (ISSCC), 68, 260\u2013262 . https:\/\/doi.org\/10.1109\/ISSCC49661.2025.10904646","DOI":"10.1109\/ISSCC49661.2025.10904646"},{"issue":"4","key":"8080_CR52","doi-asserted-by":"publisher","first-page":"995","DOI":"10.1109\/JSSC.2017.2776302","volume":"53","author":"Y Zhang","year":"2018","unstructured":"Zhang Y, Xu L, Dong Q, Wang J, Blaauw D, Sylvester D (2018) Recryptor: a reconfigurable cryptographic cortex-m0 processor with in-memory and near-memory computing for iot security. IEEE J Solid-State Circuits 53(4):995\u20131005. https:\/\/doi.org\/10.1109\/JSSC.2017.2776302","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR53","doi-asserted-by":"publisher","unstructured":"Fujiwara H, Mori H, Zhao W-C, Chuang M-C, Naous R, Chuang C-K, Hashizume T, Sun D, Lee C-F, Akarvardar K, Adham S, Chou T-L, Sinangil ME, Wang Y, Chih Y-D, Chen Y-H, Liao H-J, Chang T-YJ (2022) A 5-nm 254-tops\/w 221-tops\/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage-frequency scaling and simultaneous mac and write operations. In: 2022 IEEE International Solid-State Circuits Conference (ISSCC), 65:1\u20133. https:\/\/doi.org\/10.1109\/ISSCC42614.2022.9731754","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"issue":"9","key":"8080_CR54","doi-asserted-by":"publisher","first-page":"2817","DOI":"10.1109\/JSSC.2021.3073254","volume":"56","author":"X Si","year":"2021","unstructured":"...Si X, Tu Y-N, Huang W-H, Su J-W, Lu P-J, Wang J-H, Liu T-W, Wu S-Y, Liu R, Chou Y-C, Chung Y-L, Shih W, Lo C-C, Liu R-S, Hsieh C-C, Tang K-T, Lien N-C, Shih W-C, He Y, Li Q, Chang M-F (2021) A local computing cell and 6t sram-based computing-in-memory macro with 8-b mac operation for edge ai chips. IEEE J Solid-State Circuits 56(9):2817\u20132831. https:\/\/doi.org\/10.1109\/JSSC.2021.3073254","journal-title":"IEEE J Solid-State Circuits"},{"issue":"2","key":"8080_CR55","doi-asserted-by":"publisher","first-page":"695","DOI":"10.1109\/JSSC.2024.3433417","volume":"60","author":"H Diao","year":"2025","unstructured":"Diao H, He Y, Li X, Tang C, Jia W, Yue J, Luo H, Song J, Li X, Yang H, Jia H, Liu Y, Wang Y, Tang X (2025) A multiply-less approximate sram compute-in-memory macro for neural-network inference. IEEE J Solid-State Circuits 60(2):695\u2013706. https:\/\/doi.org\/10.1109\/JSSC.2024.3433417","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR56","doi-asserted-by":"publisher","unstructured":"Yuan Y, Zhang B, Yang Y, Luo Y, Chen Q, Lv S, Wu H, Ma C, Li M, Yue J, Wang X, Xing G, Mak P-I, Li X, Zhang F (2025) 14.5 a 28nm 192.3tflops\/w accurate\/approximate dual-mode-transpose digital 6t-sram cim macro for floating-point edge training and inference. In: 2025 IEEE International Solid-State Circuits Conference (ISSCC), 68:258\u2013260. https:\/\/doi.org\/10.1109\/ISSCC49661.2025.10904659","DOI":"10.1109\/ISSCC49661.2025.10904659"},{"key":"8080_CR57","doi-asserted-by":"publisher","unstructured":"Zhang W, Ando S, Chen Y-C, Miyagi S, Takamaeda-Yamazaki S, Yoshioka K (2025) PACiM: A Sparsity-Centric Hybrid Compute-in-Memory Architecture via Probabilistic Approximation. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3676536.3676704","DOI":"10.1145\/3676536.3676704"},{"key":"8080_CR58","doi-asserted-by":"publisher","unstructured":"Wang Y, Yang X, Qin Y, Zhao Z, Guo R, Yue Z, Han H, Wei S, Hu Y, Yin S (2024) 34.1 a 28nm 83.23tflops\/w posit-based compute-in-memory macro for high-accuracy ai applications. In: 2024 IEEE International Solid-State Circuits Conference (ISSCC), 67:566\u2013568. https:\/\/doi.org\/10.1109\/ISSCC49657.2024.10454567","DOI":"10.1109\/ISSCC49657.2024.10454567"},{"key":"8080_CR59","doi-asserted-by":"publisher","unstructured":"Wang X, Jiao T, Yang Y, Li S, Li D, Guo A, Shi Y, Tang Y, Chen J, Zhang Z, Liu Z, Liu B, Shan W, Wang X, Cai H, Zhu W, Yang J, Si X (2025) 14.3 a 28nm 17.83-to-62.84tflops\/w broadcast-alignment floating-point cim macro with non-two\u2019s-complement mac for cnns and transformers. In: 2025 IEEE International Solid-State Circuits Conference (ISSCC), 68, 254\u2013256. https:\/\/doi.org\/10.1109\/ISSCC49661.2025.10904738","DOI":"10.1109\/ISSCC49661.2025.10904738"},{"key":"8080_CR60","doi-asserted-by":"publisher","unstructured":"Yue Z, Xiang X, Wang Y, Guo R, Han H, Wei S, Hu Y, Yin S (2025) 14.4 a 51.6tflops\/w full-datapath cim macro approaching sparsity bound and \u00a12-30 loss for compound ai. In: 2025 IEEE International Solid-State Circuits Conference (ISSCC), 68:1\u20133. https:\/\/doi.org\/10.1109\/ISSCC49661.2025.10904702","DOI":"10.1109\/ISSCC49661.2025.10904702"},{"key":"8080_CR61","doi-asserted-by":"publisher","unstructured":"Sehgal R, Mehra R, Ni C, Kulkarni JP (2023) Compute-mlrom: Compute-in-multi level read only memory for energy efficient edge ai inference engines. In: ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC), 37\u201340. https:\/\/doi.org\/10.1109\/ESSCIRC59616.2023.10268726","DOI":"10.1109\/ESSCIRC59616.2023.10268726"},{"issue":"6","key":"8080_CR62","doi-asserted-by":"publisher","first-page":"1912","DOI":"10.1109\/JSSC.2023.3326955","volume":"59","author":"G Yin","year":"2024","unstructured":"Yin G, Chen Y, Zhou M, Tang W, Lee M, Yang Z, Liao T, Du X, Narayanan V, Yang H, Jia H, Liu Y, Li X (2024) Cramming more weight data onto compute-in-memory macros for high task-level energy efficiency using custom rom with 3984-kb\/mm2 density in 65-nm cmos. IEEE J Solid-State Circuits 59(6):1912\u20131925. https:\/\/doi.org\/10.1109\/JSSC.2023.3326955","journal-title":"IEEE J Solid-State Circuits"},{"key":"8080_CR63","doi-asserted-by":"publisher","unstructured":"Cheong L-A, Wang C, Zhou M, Liao T, Lee M, Ke Y, Tang W, Chen Y, Du X, Liu Y, Yang H, Li X (2024) A 28nm 166.9 tops\/w x mb\/mm2 dram-free qlc compute-in-rom macro supporting high task-level inference energy efficiency for tiny ai edge devices. In: 2024 IEEE Asian Solid-State Circuits Conference (A-SSCC), 1\u20133. https:\/\/doi.org\/10.1109\/A-SSCC60305.2024.10849083","DOI":"10.1109\/A-SSCC60305.2024.10849083"},{"key":"8080_CR64","doi-asserted-by":"publisher","unstructured":"Chen Y, Du X, Yin G, Tang W, Liu Y, Yang H, Li X (2025) 3d-metro: Deploy large-scale transformer model on a chip using transistor-less 3d-metal-rom-based compute-in-memory macro. In: Proceedings of the 30th Asia and South Pacific Design Automation Conference. ASPDAC \u201925, pp. 642\u2013647. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3658617.3697570","DOI":"10.1145\/3658617.3697570"},{"key":"8080_CR65","doi-asserted-by":"publisher","unstructured":"Yu T, Liao T, Zhou M, Chu X, Yin G, Lee M, Liu Y, Yang H, Li X (2025) Dcirom: A fully digital compute-in-rom design approach to high energy efficiency of dnn inference at task level. In: Proceedings of the 30th Asia and South Pacific Design Automation Conference. ASPDAC \u201925, pp. 100\u2013105. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3658617.3697585","DOI":"10.1145\/3658617.3697585"},{"key":"8080_CR66","doi-asserted-by":"publisher","unstructured":"Yu T, Chen Z, Chen Y, Wang S, Liu Y, Yang H, Li X (2025) Dsc-rom: A fully digital sparsity-compressed compute-in-rom architecture for on-chip deployment of large-scale dnns. In: 2025 Design, Automation & Test in Europe Conference (DATE), 1\u20136 . https:\/\/doi.org\/10.23919\/DATE64628.2025.10993132","DOI":"10.23919\/DATE64628.2025.10993132"},{"key":"8080_CR67","doi-asserted-by":"publisher","unstructured":"Yin G, Chen Y, Lee M, Du X, Ke Y, Tang W, Chen Z, Zhou M, Yue J, Yang H, Jia H, Liu Y, Li X (2024) A 28nm 8928kb\/mm$$^2$$-weight-density hybrid sram\/rom compute-in-memory architecture reducing $$>$$95% weight loading from dram. In: 2024 IEEE Custom Integrated Circuits Conference (CICC), 1\u20132. https:\/\/doi.org\/10.1109\/CICC60959.2024.10528966","DOI":"10.1109\/CICC60959.2024.10528966"},{"key":"8080_CR68","doi-asserted-by":"publisher","unstructured":"Chen Y, Yin G, Tan Z, Lee M, Yang Z, Liu Y, Yang H, Ma K, Li X (2022) Yoloc: deploy large-scale neural network by rom-based computing-in-memory using residual branch on a chip. In: Proceedings of the 59th ACM\/IEEE Design Automation Conference. DAC \u201922, pp. 1093\u20131098. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3489517.3530576","DOI":"10.1145\/3489517.3530576"},{"key":"8080_CR69","doi-asserted-by":"publisher","unstructured":"Szegedy C, Liu W, Jia Y, Sermanet P, Reed S, Anguelov D, Erhan D, Vanhoucke V, Rabinovich A (2015) Going deeper with convolutions. In: 2015 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), 1\u20139. https:\/\/doi.org\/10.1109\/CVPR.2015.7298594","DOI":"10.1109\/CVPR.2015.7298594"},{"key":"8080_CR70","doi-asserted-by":"publisher","unstructured":"Chen Y, Yin G, Lee M, Tang W, Yang Z, Liu Y, Yang H, Li X (2022) Hidden-rom: A compute-in-rom architecture to deploy large-scale neural networks on chip with flexible and scalable post-fabrication task transfer capability. In: Proceedings of the 41st IEEE\/ACM International Conference on Computer-Aided Design. ICCAD \u201922. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3508352.3549335","DOI":"10.1145\/3508352.3549335"},{"key":"8080_CR71","doi-asserted-by":"publisher","unstructured":"Ramanujan V, Wortsman M, Kembhavi A, Farhadi A, Rastegari M (2020) What\u2019s hidden in a randomly weighted neural network? In: 2020 IEEE\/CVF Conference on Computer Vision and Pattern Recognition (CVPR), 11890\u201311899. https:\/\/doi.org\/10.1109\/CVPR42600.2020.01191","DOI":"10.1109\/CVPR42600.2020.01191"},{"key":"8080_CR72","doi-asserted-by":"publisher","unstructured":"He K, Zhang X, Ren S, Sun J (2015) Delving deep into rectifiers: Surpassing human-level performance on imagenet classification. In: 2015 IEEE International Conference on Computer Vision (ICCV), 1026\u20131034. https:\/\/doi.org\/10.1109\/ICCV.2015.123","DOI":"10.1109\/ICCV.2015.123"},{"key":"8080_CR73","doi-asserted-by":"publisher","unstructured":"Wan T, Chen Y, Chen Z, Liu Y, Yang H, Li X (2025) Addr: Architecture design and model deployment optimization for hybrid sram-rom compute-in-memory. In: Proceedings of the Great Lakes Symposium on VLSI 2025. GLSVLSI \u201925, 22\u201328. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3716368.3735252","DOI":"10.1145\/3716368.3735252"},{"key":"8080_CR74","doi-asserted-by":"publisher","unstructured":"Loh GH (2008) 3d-stacked memory architectures for multi-core processors. In: 2008 International Symposium on Computer Architecture, 453\u2013464. https:\/\/doi.org\/10.1109\/ISCA.2008.15","DOI":"10.1109\/ISCA.2008.15"},{"key":"8080_CR75","doi-asserted-by":"publisher","unstructured":"KrishnanGokul Mandalsumit K, PannalaManvitha ChakrabartiChaitali SeoJae-Sun Ograsumit Y, CaoYu (2021) Siam: Chiplet-based scalable in-memory acceleration with mesh for deep neural networks. ACM Transactions on Embedded Computing Systems (TECS) https:\/\/doi.org\/10.1145\/3476999","DOI":"10.1145\/3476999"},{"key":"8080_CR76","doi-asserted-by":"publisher","unstructured":"Shao YS, Clemons J, Venkatesan R, Zimmer B, Fojtik M, Jiang N, Keller B, Klinefelter A, Pinckney N, Raina P, Tell SG, Zhang Y, Dally WJ, Emer J, Gray CT, Khailany B, Keckler SW (2019) Simba: Scaling deep-learning inference with multi-chip-module-based architecture. In: Proceedings of the 52nd Annual IEEE\/ACM International Symposium on Microarchitecture. MICRO-52, 14\u201327. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3352460.3358302","DOI":"10.1145\/3352460.3358302"},{"key":"8080_CR77","doi-asserted-by":"publisher","unstructured":"Naffziger S, Beck N, Burd T, Lepak K, Loh GH, Subramony M, White S (2021) Pioneering chiplet technology and design for the amd epyc\u2122 and ryzen\u2122 processor families : Industrial product. In: 2021 ACM\/IEEE 48th Annual International Symposium on Computer Architecture (ISCA), 57\u201370. https:\/\/doi.org\/10.1109\/ISCA52012.2021.00014","DOI":"10.1109\/ISCA52012.2021.00014"},{"key":"8080_CR78","doi-asserted-by":"publisher","unstructured":"Sang H, Wang Z, Lin N, Zhao G, Law M-K (2025) Svrom: A 9.52-mw video understanding smart vision soc with on-chip sensing and similarity-aware sram\/rom cim macro. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1\u201314 https:\/\/doi.org\/10.1109\/TVLSI.2025.3607437","DOI":"10.1109\/TVLSI.2025.3607437"},{"key":"8080_CR79","unstructured":"Li J, Shi H, Jiang X, Li Z, Xu H, Jia J (2024) QuickLLaMA: query-aware inference acceleration for large language models. https:\/\/arxiv.org\/abs\/2406.07528"},{"key":"8080_CR80","unstructured":"Xu Y, Jie Z, Dong H, Wang L, Lu X, Zhou A, Saha A, Xiong C, Sahoo D (2025) ThinK: thinner key cache by query-driven pruning. https:\/\/arxiv.org\/abs\/2407.21018"},{"key":"8080_CR81","unstructured":"Zhang Z, Sheng Y, Zhou T, Chen T, Zheng L, Cai R, Song Z, Tian Y, R\u00e9 C, Barrett C, Wang Z, Chen B (2023) H2o: heavy-hitter oracle for efficient generative inference of large language models. In: Proceedings of the 37th International Conference on Neural Information Processing Systems. NIPS \u201923. Curran Associates Inc., Red Hook, NY, USA"},{"key":"8080_CR82","unstructured":"Li Y, Huang Y, Yang B, Venkitesh B, Locatelli A, Ye H, Cai T, Lewis P, Chen D (2025) Snapkv: Llm knows what you are looking for before generation. In: Proceedings of the 38th International Conference on Neural Information Processing Systems. NIPS \u201924. Curran Associates Inc., Red Hook, NY, USA"},{"key":"8080_CR83","doi-asserted-by":"crossref","unstructured":"Xu W, Zeng W, Huang Q, Li M, Huang R (2025) UniCAIM: A Unified CAM\/CIM Architecture with Static-Dynamic KV Cache Pruning for Efficient Long-Context LLM Inference. https:\/\/arxiv.org\/abs\/2504.07479","DOI":"10.1109\/DAC63849.2025.11133273"},{"key":"8080_CR84","doi-asserted-by":"publisher","unstructured":"Su J-W, Si X, Chou Y-C, Chang T-W, Huang W-H, Tu Y-N, Liu R, Lu P-J, Liu T-W, Wang J-H, Zhang Z, Jiang H, Huang S, Lo C-C, Liu R-S, Hsieh C-C, Tang K-T, Sheu S-S, Li S-H, Lee H-Y, Chang S-C, Yu S, Chang M-F (2020) 15.2 a 28nm 64kb inference-training two-way transpose multibit 6t sram compute-in-memory macro for ai edge chips. In: 2020 IEEE International Solid-State Circuits Conference - (ISSCC), 240\u2013242. https:\/\/doi.org\/10.1109\/ISSCC19947.2020.9062949","DOI":"10.1109\/ISSCC19947.2020.9062949"},{"issue":"7","key":"8080_CR85","doi-asserted-by":"publisher","first-page":"944","DOI":"10.1109\/TC.2020.2980533","volume":"69","author":"H Jiang","year":"2020","unstructured":"Jiang H, Peng X, Huang S, Yu S (2020) Cimat: a compute-in-memory architecture for on-chip training based on transpose sram arrays. IEEE Trans Comput 69(7):944\u2013954. https:\/\/doi.org\/10.1109\/TC.2020.2980533","journal-title":"IEEE Trans Comput"},{"key":"8080_CR86","doi-asserted-by":"publisher","unstructured":"Wang J, Yang H, Deng S, Li X (2024) Cimsat: Exploiting sat analysis to attack compute-in-memory architecture defenses. In: Proceedings of the 2024 on ACM SIGSAC Conference on Computer and Communications Security. CCS \u201924, 3436\u20133450. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3658644.3690251","DOI":"10.1145\/3658644.3690251"},{"key":"8080_CR87","doi-asserted-by":"crossref","unstructured":"Sayyah Ensan S, Nagarajan K, Khan MNI, Ghosh S (2021) Scare Side channel attack on in-memory computing for reverse engineering. IEEE Trans Very Large Scale Integr (VLSI) Syst 29(12), 2040\u20132051 , 10.1109\/TVLSI.2021.3110744","DOI":"10.1109\/TVLSI.2021.3110744"},{"key":"8080_CR88","doi-asserted-by":"publisher","unstructured":"Potluri S, Aysu A (2021) Stealing neural network models through the scan chain: A new threat for ml hardware. In: 2021 IEEE\/ACM International Conference On Computer Aided Design (ICCAD), 1\u20138. https:\/\/doi.org\/10.1109\/ICCAD51958.2021.9643547","DOI":"10.1109\/ICCAD51958.2021.9643547"},{"key":"8080_CR89","doi-asserted-by":"publisher","unstructured":"Chakraborty A, Mondai A, Srivastava A (2020) Hardware-assisted intellectual property protection of deep learning models. In: 2020 57th ACM\/IEEE Design Automation Conference (DAC), 1\u20136. https:\/\/doi.org\/10.1109\/DAC18072.2020.9218651","DOI":"10.1109\/DAC18072.2020.9218651"},{"key":"8080_CR90","doi-asserted-by":"publisher","unstructured":"Huang S, Jiang H, Peng X, Li W, Yu S (2020) Xor-cim: compute-in-memory sram architecture with embedded xor encryption. In: Proceedings of the 39th International Conference on Computer-Aided Design. ICCAD \u201920. Association for Computing Machinery, New York, NY, USA. https:\/\/doi.org\/10.1145\/3400302.3415678","DOI":"10.1145\/3400302.3415678"}],"container-title":["The Journal of Supercomputing"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-025-08080-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11227-025-08080-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11227-025-08080-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,11,28]],"date-time":"2025-11-28T17:24:17Z","timestamp":1764350657000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11227-025-08080-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,11,28]]},"references-count":90,"journal-issue":{"issue":"17","published-online":{"date-parts":[[2025,11]]}},"alternative-id":["8080"],"URL":"https:\/\/doi.org\/10.1007\/s11227-025-08080-2","relation":{},"ISSN":["1573-0484"],"issn-type":[{"value":"1573-0484","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,11,28]]},"assertion":[{"value":"30 September 2025","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 November 2025","order":2,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 November 2025","order":3,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors declare no conflict of interest.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Conflict of interest"}}],"article-number":"1606"}}