{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,7,29]],"date-time":"2024-07-29T09:54:26Z","timestamp":1722246866394},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2013,8,10]],"date-time":"2013-08-10T00:00:00Z","timestamp":1376092800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["Telecommun Syst"],"published-print":{"date-parts":[[2014,3]]},"DOI":"10.1007\/s11235-013-9791-1","type":"journal-article","created":{"date-parts":[[2013,8,9]],"date-time":"2013-08-09T12:12:58Z","timestamp":1376050378000},"page":"333-344","source":"Crossref","is-referenced-by-count":1,"title":["A reconfigurable processor architecture combining multi-core and reconfigurable processing units"],"prefix":"10.1007","volume":"55","author":[{"given":"Like","family":"Yan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Binbin","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan","family":"Wen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shaobin","family":"Zhang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tianzhou","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,8,10]]},"reference":[{"issue":"6","key":"9791_CR1","doi-asserted-by":"crossref","first-page":"455","DOI":"10.1016\/j.aeue.2007.06.004","volume":"62","author":"D. Banovic","year":"2008","unstructured":"Banovic, D., & Radusinovic, I. (2008). Scheduling algorithm for VOQ switches. AE\u00dc. International Journal of Electronics and Communications, 62(6), 455\u2013458.","journal-title":"AE\u00dc. International Journal of Electronics and Communications"},{"issue":"6","key":"9791_CR2","doi-asserted-by":"crossref","first-page":"878","DOI":"10.1016\/j.compeleceng.2008.11.024","volume":"35","author":"Y. Birk","year":"2009","unstructured":"Birk, Y., & Fiksman, E. (2009). Dynamic reconfiguration architectures for multi-context FPGAs. Computers & Electrical Engineering, 35(6), 878\u2013903.","journal-title":"Computers & Electrical Engineering"},{"key":"9791_CR3","volume-title":"Proceedings of the 20th annual conference on integrated circuits and systems design","author":"C. Bobda","year":"2007","unstructured":"Bobda, C., Haller, T., Muehlbauer, F., Rech, D., & Jung, S. (2007). Design of adaptive multiprocessor on chip systems. In Proceedings of the 20th annual conference on integrated circuits and systems design. Copacabana, Rio de Janeiro."},{"key":"9791_CR4","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1109\/ISSCC.2003.1234288","volume-title":"Proc. of 2003 IEEE international solid-state circuits conference","author":"F. Campi","year":"2003","unstructured":"Campi, F., Toma, M., Lodi, A., Cappelli, A., Canegallo, R., & Guerrieri, R. (2003). A VLIW processor with reconfigurable instruction set for embedded applications. In Proc. of 2003 IEEE international solid-state circuits conference (pp. 250\u2013491)."},{"issue":"3\u20134","key":"9791_CR5","doi-asserted-by":"crossref","first-page":"161","DOI":"10.1007\/s11235-008-9137-6","volume":"40","author":"D. Dietterle","year":"2009","unstructured":"Dietterle, D., & Kraemer, R. (2009). A hardware accelerated implementation of the IEEE 802.15.3 MAC protocol. Telecommunications Systems, 40(3\u20134), 161\u2013167.","journal-title":"Telecommunications Systems"},{"key":"9791_CR6","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1109\/FPL.2006.311212","volume-title":"Proc. of 2006 international conference on field programmable logic and applications (FPL\u201906)","author":"W. Fu","year":"2006","unstructured":"Fu, W., & Compton, K. (2006). A simulation platform for reconfigurable computing research. In Proc. of 2006 international conference on field programmable logic and applications (FPL\u201906) (pp. 1\u20137)."},{"key":"9791_CR7","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1109\/FCCM.2007.49","volume-title":"Proc. of 15th annual IEEE symposium on field-programmable custom computing machines (FCCM 2007)","author":"P. Garcia","year":"2007","unstructured":"Garcia, P., & Compton, K. (2007). A reconfigurable hardware interface for a modern computing system. In Proc. of 15th annual IEEE symposium on field-programmable custom computing machines (FCCM 2007) (pp. 73\u201384)."},{"key":"9791_CR8","doi-asserted-by":"crossref","first-page":"134","DOI":"10.1109\/FPT.2002.1188674","volume-title":"Proc. of 2002 IEEE international conference on field-programmable technology (FPT 2003)","author":"D. B. Gottlieh","year":"2002","unstructured":"Gottlieh, D. B., Cook, J. J., Walstrom, J. D., Ferrera, S., & Wang, C. W. (2002). Clustered programmable-reconfigurable processors. In Proc. of 2002 IEEE international conference on field-programmable technology (FPT 2003) (pp. 134\u2013141)."},{"issue":"1","key":"9791_CR9","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1186\/1687-3963-2007-047580","volume":"2007","author":"C. Haubelt","year":"2007","unstructured":"Haubelt, C., Falk, J., Keinert, J., Schlichter, T., Streub, M., Deyhle, A., Hadert, A., & Teich, J. (2007). A SystemC-based design methodology for digital signal processing systems. EURASIP Journal on Embedded Systems, 2007(1), 15.","journal-title":"EURASIP Journal on Embedded Systems"},{"key":"9791_CR10","first-page":"12","volume-title":"Proc. of 5th annual IEEE symposium on FPGAs for custom computing machines","author":"J. R. Hauser","year":"1997","unstructured":"Hauser, J. R., & Wawrzynek, J. (1997). Garp: a MIPS processor with a reconfigurable coprocessor. In Proc. of 5th annual IEEE symposium on FPGAs for custom computing machines (pp. 12\u201321)."},{"key":"9791_CR11","first-page":"257","volume-title":"Proc. of the ACM\/SIGDA international symposium on field programmable gate arrays","author":"J. T. L. Ho","year":"2009","unstructured":"Ho, J. T. L., & Lemieux, G. G. F. (2009). PERG-Rx: a hardware pattern-matching engine supporting limited regular expressions. In Proc. of the ACM\/SIGDA international symposium on field programmable gate arrays (pp. 257\u2013260)."},{"key":"9791_CR12","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1109\/FCCM.2009.12","volume-title":"Proc. of the 2009 17th IEEE symposium on field programmable custom computing machines","author":"V. V. Kindratenko","year":"2009","unstructured":"Kindratenko, V. V., & Brunner, R. J. (2009). Accelerating cosmological data analysis with FPGAs. In Proc. of the 2009 17th IEEE symposium on field programmable custom computing machines (pp. 11\u201318)."},{"key":"9791_CR13","doi-asserted-by":"crossref","first-page":"296","DOI":"10.1109\/FCCM.2004.55","volume-title":"Proc. of the 12th annual IEEE symposium on field-programmable custom computing machines (FCCM 2004)","author":"G. Kuzmanov","year":"2004","unstructured":"Kuzmanov, G., Gaydadjiev, G., & Vassiliadis, S. (2004). The MOLEN processor prototype. In Proc. of the 12th annual IEEE symposium on field-programmable custom computing machines (FCCM 2004) (pp. 296\u2013299)."},{"key":"9791_CR14","first-page":"297","volume-title":"Proc. of the 3rd IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis","author":"S. Lin","year":"2005","unstructured":"Lin, S., Parameswaran, S. S., & Cheung, N. (2005). Novel architecture for loop acceleration: a case study. In Proc. of the 3rd IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis (pp. 297\u2013302)."},{"issue":"3","key":"9791_CR15","doi-asserted-by":"crossref","first-page":"659","DOI":"10.1145\/1142980.1142986","volume":"11","author":"R. Lysecky","year":"2006","unstructured":"Lysecky, R., Stitt, G., & Vahid, F. (2006). Warp processors. ACM Transactions on Design Automation of Electronic Systems, 11(3), 659\u2013681.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"issue":"6","key":"9791_CR16","doi-asserted-by":"crossref","first-page":"858","DOI":"10.1109\/92.974899","volume":"9","author":"R. Maestre","year":"2001","unstructured":"Maestre, R., Kurdahi, F. J., Fernandez, M., Hermida, R., Bagherzadeh, N., & Singh, H. (2001). A framework for reconfigurable computing: task scheduling and context management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 9(6), 858\u2013873.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"2","key":"9791_CR17","doi-asserted-by":"crossref","first-page":"50","DOI":"10.1109\/2.982916","volume":"35","author":"P. S. Magnusson","year":"2002","unstructured":"Magnusson, P. S., Christensson, M., Eskilson, J., Forsgren, D., Hallberg, G., Hogberg, J., Larsson, F., Moestedt, A., & Werner, B. (2002). Simics: a full system simulation platform. Computer, 35(2), 50\u201358.","journal-title":"Computer"},{"key":"9791_CR18","unstructured":"OpenCores. http:\/\/www.opencores.org\/ ."},{"key":"9791_CR19","doi-asserted-by":"crossref","unstructured":"Pande, A., & Zambreno, J. (2011). A chaotic encryption scheme for real-time embedded systems design and implementation. Telecommunication Systems, Published Online, 2 June 2011.","DOI":"10.1007\/s11235-011-9460-1"},{"key":"9791_CR20","series-title":"Lecture notes in computer science","doi-asserted-by":"crossref","first-page":"191","DOI":"10.1007\/978-3-540-25969-5_17","volume-title":"High speed networks and multimedia communications","author":"L. Peng","year":"2004","unstructured":"Peng, L., Tian, C., & Zheng, S. (2004). IRGRR: a fast scheduling scheme with less control messages for scalable crossbar switches. In Lecture notes in computer science: Vol.\u00a03079. High speed networks and multimedia communications (pp. 191\u2013202). Berlin: Springer."},{"key":"9791_CR21","doi-asserted-by":"crossref","first-page":"159","DOI":"10.1145\/1284480.1284527","volume-title":"Proc. of the 20th annual conference on integrated circuits and systems design","author":"M. M. Pereira","year":"2007","unstructured":"Pereira, M. M., Oliveira, B. C., & Silva, I. S. (2007). RoSA: a reconfigurable stream-based architecture. In Proc. of the 20th annual conference on integrated circuits and systems design (pp. 159\u2013164)."},{"key":"9791_CR22","first-page":"172","volume-title":"Proc. of the 27th annual international symposium on microarchitecture","author":"R. Rahul","year":"1994","unstructured":"Rahul, R., & Michael, D. S. (1994). A high-performance microarchitecture with hardware-programmable functional units. In Proc. of the 27th annual international symposium on microarchitecture (pp. 172\u2013180)."},{"issue":"5","key":"9791_CR23","doi-asserted-by":"crossref","first-page":"545","DOI":"10.1147\/rd.515.0545","volume":"51","author":"M. W. Riley","year":"2007","unstructured":"Riley, M. W., Warnock, J. D., & Wendel, D. F. (2007). Cell broadband engine processor: design and implementation. IBM Journal of Research and Development, 51(5), 545\u2013557.","journal-title":"IBM Journal of Research and Development"},{"key":"9791_CR24","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1145\/1723112.1723136","volume-title":"Proceedings of the 18th annual ACM\/SIGDA international symposium on field programmable gate arrays","author":"K. Rupnow","year":"2010","unstructured":"Rupnow, K., Adriaens, J., Fu, W., & Compton, K. (2010). Accurately evaluating application performance in simulated hybrid multi-tasking systems. In Proceedings of the 18th annual ACM\/SIGDA international symposium on field programmable gate arrays (pp. 135\u2013144)."},{"key":"9791_CR25","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/ASSCC.2007.4425786","volume-title":"Proc. of 2007 solid-state circuits conference (ASSCC\u2019 07)","author":"M. Shah","year":"2007","unstructured":"Shah, M., Barreh, J., Brooks, J., Golla, R., Grohoski, G., Gura, N., Hetherington, R., Jordan, P., Luttrell, M., Olson, C., Saha, B., Sheahan, D., Spracklen, L., & Wynn, A. (2007). UltraSPARC T2: a highly-threaded, power-efficient, SPARC SOC. In Proc. of 2007 solid-state circuits conference (ASSCC\u2019 07) (pp. 22\u201325)."},{"key":"9791_CR26","doi-asserted-by":"crossref","first-page":"93","DOI":"10.1145\/1289816.1289841","volume-title":"Proc. of the 5th IEEE\/ACM international conference on hardware\/software codesign and system synthesis","author":"G. Stitt","year":"2007","unstructured":"Stitt, G., & Vahid, F. (2007). Thread warping: a framework for dynamic synthesis of thread accelerators. In Proc. of the 5th IEEE\/ACM international conference on hardware\/software codesign and system synthesis (pp. 93\u201398)."},{"key":"9791_CR27","unstructured":"Thomos, C., & Kalivas, G. (2011). FPGA-based architecture and implementation techniques of a low-complexity hybrid RAKE receiver for a DS-UWB communication system. Telecommunication Systems, Published Online, 2 June 2011."},{"key":"9791_CR28","first-page":"29","volume-title":"Proc. of the 17th IEEE symposium on field programmable custom computing machines","author":"A. H. T. Tse","year":"2009","unstructured":"Tse, A. H. T., Thomas, D. B., & Luk, W. (2009). Accelerating quadrature methods for option valuation. In Proc. of the 17th IEEE symposium on field programmable custom computing machines (pp. 29\u201336)."},{"key":"9791_CR29","first-page":"214","volume-title":"Proc. of the 20th international parallel and distributed processing symposium (IPDPS 2006)","author":"S. Uhrig","year":"2006","unstructured":"Uhrig, S., Maier, S., Kuzmanov, G., & Ungerer, T. (2006). Coupling of a reconfigurable architecture and a multithreaded processor core with integrated real-time scheduling. In Proc. of the 20th international parallel and distributed processing symposium (IPDPS 2006) (pp. 214\u2013217)."},{"issue":"6","key":"9791_CR30","doi-asserted-by":"crossref","first-page":"539","DOI":"10.1587\/transele.E92.C.539","volume":"92","author":"H. M. Waidyasooriya","year":"2009","unstructured":"Waidyasooriya, H. M., Hariyama, M., & Kameyama, M. (2009). Implementation of a partially reconfigurable multi-context FPGA based on asynchronous architecture. IEICE Transactions on Electronics, 92(6), 539\u2013549.","journal-title":"IEICE Transactions on Electronics"},{"key":"9791_CR31","doi-asserted-by":"crossref","first-page":"199","DOI":"10.1145\/1216919.1216952","volume-title":"Proc. of the 2007 ACM\/SIGDA 15th international symposium on field programmable gate arrays","author":"N. Weaver","year":"2007","unstructured":"Weaver, N., Paxson, N., & Gonzalez, J. M. (2007). The shunt: an FPGA-based accelerator for network intrusion prevention. In Proc. of the 2007 ACM\/SIGDA 15th international symposium on field programmable gate arrays (pp. 199\u2013206)."},{"key":"9791_CR32","doi-asserted-by":"crossref","first-page":"126","DOI":"10.1109\/FPGA.1996.564773","volume-title":"Proc. of 1996 IEEE symposium on FPGAs for custom computing machines","author":"R. D. Wittig","year":"1996","unstructured":"Wittig, R. D., & Chow, P. (1996). OneChip: an FPGA processor with reconfigurable logic. In Proc. of 1996 IEEE symposium on FPGAs for custom computing machines (pp. 126\u2013135)."},{"key":"9791_CR33","unstructured":"Xilinx Inc. (2007). Virtex-5 FPGA configuration user guide. http:\/\/www.xilinx.com\/support\/documentation\/virtex-5_user_guides.htm ."},{"key":"9791_CR34","first-page":"225","volume-title":"Proc. of the 27th annual international symposium on computer architecture","author":"Z. A. Ye","year":"2000","unstructured":"Ye, Z. A., Moshovos, A., Hauck, S., & Banerjee, P. (2000). CHIMAERA: a high-performance architecture with a tightly-coupled reconfigurable functional unit. In Proc. of the 27th annual international symposium on computer architecture (pp. 225\u2013235)."}],"container-title":["Telecommunication Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11235-013-9791-1.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11235-013-9791-1\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11235-013-9791-1","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,20]],"date-time":"2019-07-20T15:01:20Z","timestamp":1563634880000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11235-013-9791-1"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,8,10]]},"references-count":34,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,3]]}},"alternative-id":["9791"],"URL":"https:\/\/doi.org\/10.1007\/s11235-013-9791-1","relation":{},"ISSN":["1018-4864","1572-9451"],"issn-type":[{"value":"1018-4864","type":"print"},{"value":"1572-9451","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,8,10]]}}}