{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,24]],"date-time":"2025-10-24T16:41:43Z","timestamp":1761324103070,"version":"3.37.3"},"reference-count":42,"publisher":"Springer Science and Business Media LLC","issue":"5","license":[{"start":{"date-parts":[[2017,4,22]],"date-time":"2017-04-22T00:00:00Z","timestamp":1492819200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"},{"start":{"date-parts":[[2017,4,22]],"date-time":"2017-04-22T00:00:00Z","timestamp":1492819200000},"content-version":"vor","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS 1115284","CNS 1218693"],"award-info":[{"award-number":["CNS 1115284","CNS 1218693"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CPS 1239135","CNS 1409175"],"award-info":[{"award-number":["CPS 1239135","CNS 1409175"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CPS 1446631"],"award-info":[{"award-number":["CPS 1446631"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000181","name":"Air Force Office of Scientific Research","doi-asserted-by":"publisher","award":["FA9550-14-1-0161"],"award-info":[{"award-number":["FA9550-14-1-0161"]}],"id":[{"id":"10.13039\/100000181","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000183","name":"Army Research Office","doi-asserted-by":"publisher","award":["FA9550-14-1-0161"],"award-info":[{"award-number":["FA9550-14-1-0161"]}],"id":[{"id":"10.13039\/100000183","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002463","name":"General Motors Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002463","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Real-Time Syst"],"published-print":{"date-parts":[[2017,9]]},"DOI":"10.1007\/s11241-017-9272-9","type":"journal-article","created":{"date-parts":[[2017,4,22]],"date-time":"2017-04-22T07:48:48Z","timestamp":1492847328000},"page":"709-759","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":29,"title":["Attacking the one-out-of-m multicore problem by combining hardware management with mixed-criticality provisioning"],"prefix":"10.1007","volume":"53","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-5395-3724","authenticated-orcid":false,"given":"Namhoon","family":"Kim","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Bryan C.","family":"Ward","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Micaiah","family":"Chisholm","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James H.","family":"Anderson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"F. Donelson","family":"Smith","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,4,22]]},"reference":[{"key":"9272_CR1","doi-asserted-by":"crossref","unstructured":"Alhammad A, Pellizzoni R (2016) Trading cores for memory bandwidth in real-time systems. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 317\u2013327","DOI":"10.1109\/RTAS.2016.7461364"},{"key":"9272_CR2","doi-asserted-by":"crossref","unstructured":"Alhammad A, Wasly S, Pellizzoni R (2015) Memory efficient global scheduling of real-time tasks. In: Proceedings of the 21th IEEE real-time and embedded technology and applications symposium, pp 285\u2013296","DOI":"10.1109\/RTAS.2015.7108452"},{"key":"9272_CR3","unstructured":"Altmeyer S, Douma R, Lunniss W, Davis R (2014) Evaluation of cache partitioning for hard real-time systems. In: Proceedings of the 26th euromicro conference on real-time systems, pp 15\u201326"},{"key":"9272_CR4","unstructured":"Audsley N (2013) Memory architecture for NoC-based real-time mixed criticality systems. In: Proceedings of the 1st international workshop on mixed criticality systems, pp 37\u201342"},{"key":"9272_CR5","doi-asserted-by":"crossref","unstructured":"Baker T, Shaw A (1988) The cyclic executive model and ADA. In: Proceedings of the 9th IEEE real-time systems symposium, pp 120\u2013129","DOI":"10.1109\/REAL.1988.51108"},{"key":"9272_CR6","unstructured":"Brandenburg B (2011) Scheduling and locking in multiprocessor real-time operating systems. PhD thesis, University of North Carolina, Chapel Hill, NC"},{"key":"9272_CR7","doi-asserted-by":"crossref","unstructured":"Bui B, Caccamo M, Sha L, Martinez J (2008) Impact of cache partitioning on multi-tasking real time embedded systems. In: Proceedings of the 14th IEEE international conference on embedded and real-time computing systems and applications, pp 101\u2013110","DOI":"10.1109\/RTCSA.2008.42"},{"key":"9272_CR8","volume-title":"Mixed criticality systems \u2014 a review","author":"A Burns","year":"2016","unstructured":"Burns A, Davis R (2016) Mixed criticality systems \u2014 a review. Department of Computer Science, University of York, Tech. rep"},{"key":"9272_CR9","unstructured":"Campoy M, Ivars A, Mataix J (2001) Static use of locking caches in multitask preemptive real-time systems. In: Proceedings of IEEE\/IEE real-time embedded systems workshop, pp 1283\u20131286"},{"key":"9272_CR10","unstructured":"Certification Authorities Software Team (CAST) (2014) Position paper CAST-32: multi-core processors"},{"key":"9272_CR11","unstructured":"Certification Authorities Software Team (CAST) (2016) Position paper CAST-32A: multi-core processors. \n                    https:\/\/www.faa.gov\/aircraft\/air_cert\/design_approvals\/air_software\/cast\/cast_papers\/media\/cast-32A.pdf"},{"key":"9272_CR12","doi-asserted-by":"crossref","unstructured":"Chisholm M, Ward B, Kim N, Anderson J (2015) Cache sharing and isolation tradeoffs in multicore mixed-criticality systems. In: Proceedings of the 36th IEEE real-time systems symposium, pp 305\u2013316","DOI":"10.1109\/RTSS.2015.36"},{"key":"9272_CR13","doi-asserted-by":"crossref","unstructured":"Chisholm M, Kim N, Ward B, Otterness N, Anderson J, Smith F (2016) Reconciling the tension between hardware isolation and data sharing in mixed-criticality, multicore systems. In: Proceedings of the 37th IEEE real-time symposium, pp 57\u201368","DOI":"10.1109\/RTSS.2016.015"},{"key":"9272_CR14","doi-asserted-by":"publisher","first-page":"133","DOI":"10.1007\/s11241-007-9042-1","volume":"38","author":"U Devi","year":"2008","unstructured":"Devi U, Anderson J (2008) Tardiness bounds under global EDF scheduling on a multiprocessor. R-Time Syst 38:133\u2013189","journal-title":"R-Time Syst"},{"key":"9272_CR15","doi-asserted-by":"crossref","unstructured":"Giannopoulou G, Stoimenov N, Huang P, Thiele L (2013) Scheduling of mixed-criticality applications on resource-sharing multicore systems. In: Proceedings of the 13th ACM international conference on embedded software, pp 1\u201315","DOI":"10.1109\/EMSOFT.2013.6658595"},{"key":"9272_CR16","doi-asserted-by":"crossref","unstructured":"Hassan M, Patel H (2016) Criticality- and requirement-aware bus arbitration for multi-core mixed criticality systems. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 73\u201383","DOI":"10.1109\/RTAS.2016.7461327"},{"key":"9272_CR17","doi-asserted-by":"crossref","unstructured":"Hassan M, Patel H, Pellizzoni R (2015) A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems. In: Proceedings of the 21th IEEE real-time and embedded technology and applications symposium, pp 307\u2013316","DOI":"10.1109\/RTAS.2015.7108454"},{"key":"9272_CR18","doi-asserted-by":"crossref","unstructured":"Herman J, Kenna C, Mollison M, Anderson J, Johnson D (2012) RTOS support for multicore mixed-criticality systems. In: Proceedings of the 18th IEEE real-time and embedded technology and applications symposium, pp 197\u2013208","DOI":"10.1109\/RTAS.2012.24"},{"key":"9272_CR19","doi-asserted-by":"crossref","unstructured":"Jalle J, Quinones E, Abella J, Fossati L, Zulianello M, Cazorla F (2014) A dual-criticality memory controller (DCmc) proposal and evaluation of a space case study. In: Proceedings of the 35th IEEE real-time systems symposium, pp 207\u2013217","DOI":"10.1109\/RTSS.2014.23"},{"key":"9272_CR20","doi-asserted-by":"publisher","first-page":"338","DOI":"10.1145\/138873.138876","volume":"10","author":"R Kessler","year":"1992","unstructured":"Kessler R, Hill M (1992) Page placement algorithms for large real-indexed caches. ACM Trans Comput Syst 10:338\u2013359","journal-title":"ACM Trans Comput Syst"},{"key":"9272_CR21","doi-asserted-by":"crossref","unstructured":"Kim H, Kandhalu A, Rajkumar R (2013) A coordinated approach for practical OS-level cache management in multi-core real-time systems. In: Proceedings of the 25th euromicro conference on real-time systems, pp 80\u201389","DOI":"10.1109\/ECRTS.2013.19"},{"key":"9272_CR22","doi-asserted-by":"crossref","unstructured":"Kim H, Niz DD, Andersson B, Klein M, Mutlu O, Rajkumar R (2014) Bounding memory interference delay in COTS-based multi-core systems. In: Proceedings of the 20th IEEE real-time and embedded technology and applications symposium, pp 145\u2013154","DOI":"10.1109\/RTAS.2014.6925998"},{"key":"9272_CR23","doi-asserted-by":"crossref","unstructured":"Kim H, Broman D, Lee E, Zimmer M, Shrivastava A, Oh J (2015) A predictable and command-level priority-based DRAM controller for mixed-criticality systems. In: Proceedings of the 21th IEEE real-time and embedded technology and applications symposium, pp 317\u2013326","DOI":"10.1109\/RTAS.2015.7108455"},{"key":"9272_CR24","doi-asserted-by":"crossref","unstructured":"Kim N, Ward B, Chisholm M, Fu C, Anderson J, Smith F (2016) Attacking the one-out-of-$$m$$ multicore problem by combining hardware management with mixed-criticality provisioning. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 149\u2013160","DOI":"10.1109\/RTAS.2016.7461323"},{"key":"9272_CR25","doi-asserted-by":"crossref","unstructured":"Kim N, Chisholm M, Otterness N, Anderson J, Smith F (2017a) Allowing shared libraries while supporting hardware isolation in multicore real-time systems. In: Proceedings of the 23rd IEEE Real-Time and Embedded Technology and Applications Symposium (to appear)","DOI":"10.1109\/RTAS.2017.14"},{"key":"9272_CR26","doi-asserted-by":"crossref","unstructured":"Kim N, Ward B, Chisholm M, Fu C, Anderson J, Smith F (2017b) Attacking the one-out-of-$$m$$ multicore problem by combining hardware management with mixed-criticality provisioning (full version). Available at URL: \n                    http:\/\/www.cs.unc.edu\/anderson\/papers.html","DOI":"10.1109\/RTAS.2016.7461323"},{"key":"9272_CR27","doi-asserted-by":"crossref","unstructured":"Kirk D (1989) SMART (strategic memory allocation for real-time) cache design. In: Proceedings of the 10th IEEE real-time systems symposium, pp 229\u2013237","DOI":"10.1109\/REAL.1989.63574"},{"key":"9272_CR28","unstructured":"Kotaba O, Nowotsch J, Paulitsch M, Petters S, Theiling H (2013) Multicore in real-time systems \u2013 temporal isolation challenges due to shared resources. In: Proceedings of the international workshop on industry-driven approaches for cost-effective certification of safety-critical, mixed-criticality systems"},{"key":"9272_CR29","unstructured":"Krishnapillai Y, Wu Z, Pellizzoni R (2014) ROC: A rank-switching, open-row DRAM controller for time-predictable systems. In: Proceedings of the 26th euromicro conference on real-time systems, pp 27\u201338"},{"key":"9272_CR30","unstructured":"Kroft D (1981) Lockup-free instruction fetch\/prefetch cache organization. In: Proceedings of the 8th annual symposium on computer architecture, pp 81\u201387"},{"key":"9272_CR31","doi-asserted-by":"crossref","unstructured":"Liu L, Cui Z, Xing M, Bao Y, Chen M, Wu C (2012) A software memory partition approach for eliminating bank-level interference in multicore systems. In: Proceedings of the 21st international conference on parallel architectures and compilation techniques, pp 367\u2013376","DOI":"10.1145\/2370816.2370869"},{"key":"9272_CR32","doi-asserted-by":"crossref","unstructured":"Mills A, Anderson J (2011) A multiprocessor server-based scheduler for soft real-time tasks with stochastic execution demand. In: Proceedings of the 17th IEEE international conference on embedded and real-time computing systems and applications, pp 207\u2013217","DOI":"10.1109\/RTCSA.2011.30"},{"key":"9272_CR33","doi-asserted-by":"crossref","unstructured":"Mollison M, Erickson J, Anderson J, Baruah S, Scoredos J (2010) Mixed criticality real-time scheduling for multicore systems. In: Proceedings of the 7th IEEE international conferences on embedded software and systems, pp 1864\u20131871","DOI":"10.1109\/CIT.2010.320"},{"key":"9272_CR34","doi-asserted-by":"crossref","unstructured":"Musmanno J (2003) Data intensive systems (DIS) benchmark performance summary","DOI":"10.21236\/ADA418752"},{"key":"9272_CR35","doi-asserted-by":"crossref","unstructured":"Pellizzoni R, Schranzhofer A, Chen J, Caccamo M, Thiele L (2010) Worst case delay analysis for memory interference in multicore systems. In: 2010 design, automation test in Europe conference exhibition, pp 741\u2013746","DOI":"10.1109\/DATE.2010.5456952"},{"key":"9272_CR36","doi-asserted-by":"crossref","unstructured":"Tabish R, Mancuso R, Wasly S, Alhammad A, Phatak S, Pellizzoni R, Caccamo M (2016) A real-time scratchpad-centric OS for multi-core embedded systems. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 1\u201311","DOI":"10.1109\/RTAS.2016.7461321"},{"key":"9272_CR37","doi-asserted-by":"crossref","unstructured":"Valsan P, Yun H, Farshchi F (2016) Taming non-blocking caches to improve isolation in multicore real-time systems. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 161\u2013172","DOI":"10.1109\/RTAS.2016.7461361"},{"key":"9272_CR38","doi-asserted-by":"crossref","unstructured":"Vestal S (2007) Preemptive scheduling of multi-criticality systems with varying degrees of execution time assurance. In: Proceedings of the 28th IEEE real-time systems symposium, pp 239\u2013243","DOI":"10.1109\/RTSS.2007.47"},{"key":"9272_CR39","unstructured":"Ward B, Herman J, Kenna C, Anderson J (2013) Making shared caches more predictable on multicore platforms. In: Proceedings of the 25th euromicro conference on real-time systems, pp 157\u2013167"},{"key":"9272_CR40","doi-asserted-by":"crossref","unstructured":"Xu M, Phan LTX, Choi HY, Lee I (2016) Analysis and implementation of global preemptive fixed-priority scheduling with dynamic cache allocation. In: Proceedings of the 22nd IEEE real-time and embedded technology and applications symposium, pp 123\u2013134","DOI":"10.1109\/RTAS.2016.7461322"},{"key":"9272_CR41","doi-asserted-by":"crossref","unstructured":"Yun H, Yao G, Pellizzoni R, Caccamo M, Sha L (2012) Memory access control in multiprocessor for real-time systems with mixed criticality. In: Proceedings of the 24th euromicro conference on real-time systems, pp 299\u2013308","DOI":"10.1109\/ECRTS.2012.32"},{"key":"9272_CR42","doi-asserted-by":"crossref","unstructured":"Yun H, Mancuso R, Wu Z, Pellizzoni R (2014) PALLOC: DRAM bank-aware memory allocator for performance isolation on multicoore platforms. In: Proceedings of the 20th IEEE real-time and embedded technology and applications symposium, pp 155\u2013166","DOI":"10.1109\/RTAS.2014.6925999"}],"container-title":["Real-Time Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11241-017-9272-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-017-9272-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-017-9272-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,17]],"date-time":"2020-05-17T14:04:17Z","timestamp":1589724257000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11241-017-9272-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4,22]]},"references-count":42,"journal-issue":{"issue":"5","published-print":{"date-parts":[[2017,9]]}},"alternative-id":["9272"],"URL":"https:\/\/doi.org\/10.1007\/s11241-017-9272-9","relation":{},"ISSN":["0922-6443","1573-1383"],"issn-type":[{"type":"print","value":"0922-6443"},{"type":"electronic","value":"1573-1383"}],"subject":[],"published":{"date-parts":[[2017,4,22]]},"assertion":[{"value":"22 April 2017","order":1,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}