{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,8]],"date-time":"2025-11-08T23:04:36Z","timestamp":1762643076348,"version":"3.37.3"},"reference-count":98,"publisher":"Springer Science and Business Media LLC","issue":"4","license":[{"start":{"date-parts":[[2024,6,28]],"date-time":"2024-06-28T00:00:00Z","timestamp":1719532800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"},{"start":{"date-parts":[[2024,6,28]],"date-time":"2024-06-28T00:00:00Z","timestamp":1719532800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"funder":[{"DOI":"10.13039\/100005156","name":"Alexander von Humboldt-Stiftung","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100005156","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100005713","name":"Technische Universit\u00e4t M\u00fcnchen","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100005713","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["Real-Time Syst"],"published-print":{"date-parts":[[2024,12]]},"abstract":"<jats:title>Abstract<\/jats:title><jats:p>Cache partitioning is a technique to reduce interference among tasks running on the processors with shared caches. To make this technique effective, cache segments should be allocated to tasks that will benefit the most from having their data and instructions stored in the cache. The requests for cached data and instructions can be retrieved faster from the cache memory instead of fetching them from the main memory, thereby reducing overall execution time. The existing partitioning schemes for real-time systems divide the available cache among the tasks to guarantee their schedulability as the sole and primary optimization criterion. However, it is also preferable, particularly in systems with power constraints or mixed criticalities where low- and high-criticality workloads are executing alongside, to reduce the total cache usage for real-time tasks. Cache minimization as part of design space exploration can also help in achieving optimal system performance and resource utilization in embedded systems. In this paper, we develop optimization algorithms for cache partitioning that, besides ensuring schedulability, also minimize cache usage. We consider both preemptive and non-preemptive scheduling policies on single-processor systems with fixed- and dynamic-priority scheduling algorithms (<jats:italic>Rate Monotonic<\/jats:italic> (<jats:italic>RM<\/jats:italic>) and <jats:italic>Earliest Deadline First<\/jats:italic> (<jats:italic>EDF<\/jats:italic>), respectively). For preemptive scheduling, we formulate the problem as an integer quadratically constrained program and propose an efficient heuristic achieving near-optimal solutions. For non-preemptive scheduling, we combine linear and binary search techniques with different fixed-priority schedulability tests and Quick Processor-demand Analysis (QPA) for EDF. Our experiments based on synthetic task sets with parameters from real-world embedded applications show that the proposed heuristic: (i) achieves an average optimality gap of 0.79% within 0.1\u00d7 run time of a mathematical programming solver and (ii) reduces average cache usage by 39.15% compared to existing cache partitioning approaches. Besides, we find that for large task sets with high utilization, non-preemptive scheduling can use less cache than preemptive to guarantee schedulability.<\/jats:p>","DOI":"10.1007\/s11241-024-09423-7","type":"journal-article","created":{"date-parts":[[2024,6,28]],"date-time":"2024-06-28T07:02:04Z","timestamp":1719558124000},"page":"625-664","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":3,"title":["Minimizing cache usage with fixed-priority and earliest deadline first scheduling"],"prefix":"10.1007","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9764-6259","authenticated-orcid":false,"given":"Binqi","family":"Sun","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tomasz","family":"Kloda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergio Arribas","family":"Garcia","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Giovani","family":"Gracioli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marco","family":"Caccamo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2024,6,28]]},"reference":[{"key":"9423_CR1","doi-asserted-by":"crossref","unstructured":"Albonesi D (1999) Selective cache ways: on-demand cache resource allocation. In: ACM\/IEEE International Symposium on Microarchitecture, pp 248\u2013259","DOI":"10.1109\/MICRO.1999.809463"},{"key":"9423_CR2","doi-asserted-by":"crossref","unstructured":"Altmeyer S, Burgui\u00e8re C (2009) A new notion of useful cache block to improve the bounds of cache-related preemption delay. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 109\u2013118","DOI":"10.1109\/ECRTS.2009.21"},{"key":"9423_CR3","doi-asserted-by":"crossref","unstructured":"Altmeyer S, Davis RI, Maiza C (2011) Cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. In: IEEE Real-Time Systems Symposium (RTSS), pp 261\u2013271","DOI":"10.1109\/RTSS.2011.31"},{"issue":"5","key":"9423_CR4","doi-asserted-by":"publisher","first-page":"499","DOI":"10.1007\/s11241-012-9152-2","volume":"48","author":"S Altmeyer","year":"2012","unstructured":"Altmeyer S, Davis RI, Maiza C (2012) Improved cache related pre-emption delay aware response time analysis for fixed priority pre-emptive systems. Real-Time Syst 48(5):499\u2013526","journal-title":"Real-Time Syst"},{"issue":"5","key":"9423_CR5","doi-asserted-by":"publisher","first-page":"598","DOI":"10.1007\/s11241-015-9246-8","volume":"52","author":"S Altmeyer","year":"2016","unstructured":"Altmeyer S, Douma R, Lunniss W et al (2016) On the effectiveness of cache partitioning in hard real-time systems. Real-Time Syst 52(5):598\u2013643","journal-title":"Real-Time Syst"},{"key":"9423_CR6","doi-asserted-by":"crossref","unstructured":"Audsley N, Burns A, Richardson M, et\u00a0al (1991) Hard real-time scheduling: The deadline monotonic approach. In: IEEE Workshop on Real-Time Operating Systems and Software","DOI":"10.1016\/S1474-6670(17)51283-5"},{"key":"9423_CR7","doi-asserted-by":"crossref","unstructured":"Baker TP (1990) A stack-based resource allocation policy for realtime processes. In: IEEE Real-Time Systems Symposium (RTSS), pp 191\u2013200","DOI":"10.1109\/REAL.1990.128747"},{"key":"9423_CR8","doi-asserted-by":"publisher","first-page":"67","DOI":"10.1007\/BF00365393","volume":"3","author":"TP Baker","year":"1991","unstructured":"Baker TP (1991) Stack-based scheduling of realtime processes. Real-Time Syst 3:67\u201399","journal-title":"Real-Time Syst"},{"key":"9423_CR9","doi-asserted-by":"publisher","first-page":"517","DOI":"10.1007\/s11241-011-9137-6","volume":"47","author":"S Baruah","year":"2011","unstructured":"Baruah S (2011) Efficient computation of response time bounds for preemptive uniprocessor deadline monotonic scheduling. Real-Time Syst 47:517\u2013533","journal-title":"Real-Time Syst"},{"key":"9423_CR10","doi-asserted-by":"crossref","unstructured":"Baruah S, Chakraborty S (2006) Schedulability analysis of non-preemptive recurring real-time tasks. In: IEEE International Parallel & Distributed Processing Symposium","DOI":"10.1109\/IPDPS.2006.1639406"},{"key":"9423_CR11","unstructured":"Baruah S, Ekberg P (2021) An ILP representation of response-time analysis. https:\/\/research.engineering.wustl.edu\/~baruah\/Submitted\/2021-ILP-RTA.pdf"},{"key":"9423_CR12","doi-asserted-by":"crossref","unstructured":"Baruah S, Mok A, Rosier L (1990a) Preemptively scheduling hard-real-time sporadic tasks on one processor. In: IEEE Real-Time Systems Symposium (RTSS), pp 182\u2013190","DOI":"10.1109\/REAL.1990.128746"},{"issue":"4","key":"9423_CR13","doi-asserted-by":"publisher","first-page":"301","DOI":"10.1007\/BF01995675","volume":"2","author":"SK Baruah","year":"1990","unstructured":"Baruah SK, Rosier LE, Howell RR (1990) Algorithms and complexity concerning the preemptive scheduling of periodic, real-time tasks on one processor. Real-Time Syst 2(4):301\u2013324","journal-title":"Real-Time Syst"},{"key":"9423_CR14","unstructured":"Bastoni A, Brandenburg B, Anderson J (2010) Cache-related preemption and migration delays: empirical approximation and impact on schedulability. In: OSPERT, pp 33\u201344"},{"key":"9423_CR15","doi-asserted-by":"crossref","unstructured":"Bienia C, Kumar S, Singh JP, et\u00a0al (2008) The parsec benchmark suite: Characterization and architectural implications. In: International Conference on Parallel Architectures and Compilation Techniques, pp 72\u201381","DOI":"10.1145\/1454115.1454128"},{"issue":"1","key":"9423_CR16","doi-asserted-by":"publisher","first-page":"129","DOI":"10.1007\/s11241-005-0507-9","volume":"30","author":"E Bini","year":"2005","unstructured":"Bini E, Buttazzo GC (2005) Measuring the performance of schedulability tests. Real-Time Syst 30(1):129\u2013154","journal-title":"Real-Time Syst"},{"key":"9423_CR17","doi-asserted-by":"crossref","unstructured":"Bini E, Parri A, Dossena G (2015) A quadratic-time response time upper bound with a tightness property. In: IEEE Real-Time Systems Symposium (RTSS), pp 13\u201322","DOI":"10.1109\/RTSS.2015.9"},{"key":"9423_CR18","unstructured":"Bril R, Lukkien J, Davis R, et\u00a0al (2006) Message response time analysis for ideal controller area network (CAN) refuted. In: International Workshop on Real-Time Networks"},{"key":"9423_CR19","doi-asserted-by":"crossref","unstructured":"Br\u00fcggen G, Chen JJ, Huang WH (2015) Schedulability and optimization analysis for non-preemptive static priority scheduling based on task utilization and blocking factors. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 90\u2013101","DOI":"10.1109\/ECRTS.2015.16"},{"key":"9423_CR20","doi-asserted-by":"crossref","unstructured":"Bui BD, Caccamo M, Sha L, et\u00a0al (2008) Impact of cache partitioning on multi-tasking real time embedded systems. In: IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp 101\u2013110","DOI":"10.1109\/RTCSA.2008.42"},{"issue":"1","key":"9423_CR21","doi-asserted-by":"publisher","first-page":"74","DOI":"10.5626\/JCSE.2008.2.1.074","volume":"2","author":"A Burns","year":"2008","unstructured":"Burns A, Baruah S (2008) Sustainability in real-time scheduling. J Comput Sci Eng 2(1):74\u201397","journal-title":"J Comput Sci Eng"},{"key":"9423_CR22","doi-asserted-by":"crossref","unstructured":"Busquets-Mataix J, Serrano J, Ors R, et\u00a0al (1996a) Adding instruction cache effect to schedulability analysis of preemptive real-time systems. In: Real-Time Technology and Applications, pp 204\u2013212","DOI":"10.1109\/RTTAS.1996.509537"},{"key":"9423_CR23","doi-asserted-by":"crossref","unstructured":"Busquets-Mataix J, Serrano-Martin J, Ors-Carot R, et\u00a0al (1996b) Adding instruction cache effect to an exact schedulability analysis of preemptive real-time systems. In: Euromicro Workshop on Real-Time Systems, pp 271\u2013276","DOI":"10.1109\/EMWRTS.1996.557940"},{"key":"9423_CR24","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1023\/B:TIME.0000048932.30002.d9","volume":"29","author":"G Buttazzo","year":"2005","unstructured":"Buttazzo G (2005) Rate monotonic vs. EDF: Judgment day. Real-Time Syst 29:5\u201326","journal-title":"Real-Time Syst"},{"key":"9423_CR25","doi-asserted-by":"crossref","unstructured":"Calandrino JM, Anderson JH (2008) Cache-aware real-time scheduling on multicore platforms: Heuristics and a case study. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 299\u2013308","DOI":"10.1109\/ECRTS.2008.10"},{"key":"9423_CR26","doi-asserted-by":"crossref","unstructured":"Cavicchio J, Tessler C, Fisher N (2015) Minimizing cache overhead via loaded cache blocks and preemption placement. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 163\u2013173","DOI":"10.1109\/ECRTS.2015.22"},{"key":"9423_CR27","doi-asserted-by":"crossref","unstructured":"Chen G, Huang K, Huang J, et\u00a0al (2013) Cache partitioning and scheduling for energy optimization of real-time MPSoCs. In: IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp 35\u201341","DOI":"10.1109\/ASAP.2013.6567548"},{"key":"9423_CR28","doi-asserted-by":"crossref","unstructured":"Cheng SW, Chen JJ, Reineke J, et\u00a0al (2017) Memory bank partitioning for fixed-priority tasks in a multi-core system. In: IEEE Real-Time Systems Symposium (RTSS), pp 209\u2013219","DOI":"10.1109\/RTSS.2017.00027"},{"key":"9423_CR29","doi-asserted-by":"crossref","unstructured":"Cinque M, De\u00a0Tommasi G, Dubbioso S, et\u00a0al (2022) RPUGuard: Real-time processing unit virtualization for mixed-criticality applications. In: European Dependable Computing Conference, pp 97\u2013104","DOI":"10.1109\/EDCC57035.2022.00025"},{"key":"9423_CR30","doi-asserted-by":"crossref","unstructured":"Davare A, Zhu Q, Di\u00a0Natale M, et\u00a0al (2007) Period optimization for hard real-time distributed automotive systems. In: ACM\/IEEE Design Automation Conference (DAC), pp 278\u2013283","DOI":"10.1109\/DAC.2007.375172"},{"key":"9423_CR31","doi-asserted-by":"crossref","unstructured":"Davis R, Burns A (2008) Response time upper bounds for fixed priority real-time systems. In: IEEE Real-Time Systems Symposium (RTSS), pp 407\u2013418","DOI":"10.1109\/RTSS.2008.18"},{"issue":"1","key":"9423_CR32","doi-asserted-by":"publisher","first-page":"8","DOI":"10.1145\/2597457.2597458","volume":"11","author":"RI Davis","year":"2014","unstructured":"Davis RI (2014) A review of fixed priority and EDF scheduling for hard real-time uniprocessor systems. SIGBED Rev 11(1):8\u201319","journal-title":"SIGBED Rev"},{"issue":"3","key":"9423_CR33","doi-asserted-by":"publisher","first-page":"239","DOI":"10.1007\/s11241-007-9012-7","volume":"35","author":"RI Davis","year":"2007","unstructured":"Davis RI, Burns A, Bril RJ et al (2007) Controller area network (CAN) schedulability analysis: refuted, revisited and revised. Real-Time Syst 35(3):239\u2013272","journal-title":"Real-Time Syst"},{"key":"9423_CR34","unstructured":"Durrieu G, Faug\u00e8re M, Girbal S, et\u00a0al (2014) Predictable flight management system implementation on a multicore processor. In: Embedded Real Time Software"},{"issue":"5","key":"9423_CR35","doi-asserted-by":"publisher","first-page":"65","DOI":"10.1109\/MDAT.2016.2594790","volume":"33","author":"R Ernst","year":"2016","unstructured":"Ernst R, Di Natale M (2016) Mixed criticality systems\u2013a history of misconceptions? IEEE Design Test 33(5):65\u201374","journal-title":"IEEE Design Test"},{"key":"9423_CR36","unstructured":"Farshchi F, Valsan PK, Mancuso R, et\u00a0al (2018) Deterministic memory abstraction and supporting multicore system architecture. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 1:1\u20131:25"},{"key":"9423_CR37","unstructured":"George L, Rivierre N, Spuri M (1996) Preemptive and non-preemptive real-time uniprocessor scheduling. https:\/\/inria.hal.science\/inria-00073732"},{"key":"9423_CR38","doi-asserted-by":"crossref","unstructured":"Gracioli G, Fr\u00f6hlich AA (2013) An experimental evaluation of the cache partitioning impact on multicore real-time schedulers. In: International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA), pp 72\u201381","DOI":"10.1109\/RTCSA.2013.6732205"},{"issue":"2","key":"9423_CR39","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2830555","volume":"48","author":"G Gracioli","year":"2015","unstructured":"Gracioli G, Alhammad A, Mancuso R et al (2015) A survey on cache management mechanisms for real-time embedded systems. ACM Comput Surv 48(2):1\u201336","journal-title":"ACM Comput Surv"},{"key":"9423_CR40","unstructured":"Gracioli G, Tabish R, Mancuso R, et\u00a0al (2019) Designing mixed criticality applications on modern heterogeneous MPSoC Platforms. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 27:1\u201327:25"},{"key":"9423_CR41","doi-asserted-by":"crossref","unstructured":"Griffin D, Bate I, Davis RI (2020) Generating utilization vectors for the systematic evaluation of schedulability tests. In: IEEE Real-Time Systems Symposium (RTSS), pp 76\u201388","DOI":"10.1109\/RTSS49844.2020.00018"},{"key":"9423_CR42","doi-asserted-by":"crossref","unstructured":"Guan N, Stigge M, Yi W, et\u00a0al (2009) Cache-aware scheduling and analysis for multicores. In: ACM International Conference on Embedded Software, pp 245\u2013254","DOI":"10.1145\/1629335.1629369"},{"key":"9423_CR43","doi-asserted-by":"crossref","unstructured":"Guo Z, Zhang Y, Wang L, et\u00a0al (2017) Work-in-progress: Cache-aware partitioned EDF scheduling for multi-core real-time systems. In: IEEE Real-Time Systems Symposium (RTSS), pp 384\u2013386","DOI":"10.1109\/RTSS.2017.00054"},{"key":"9423_CR44","doi-asserted-by":"crossref","unstructured":"Guo Z, Yang K, Yao F, et\u00a0al (2020) Inter-task cache interference aware partitioned real-time scheduling. In: ACM Symposium on Applied Computing (SAC), pp 218\u2013226","DOI":"10.1145\/3341105.3374014"},{"key":"9423_CR45","unstructured":"Gurobi Optimization, LLC (2022) Gurobi Optimizer Reference Manual. https:\/\/www.gurobi.com"},{"key":"9423_CR46","volume-title":"Computer architecture. A quantitative approach","author":"JL Hennessy","year":"2011","unstructured":"Hennessy JL, Patterson DA (2011) Computer architecture. A quantitative approach, 5th edn. Morgan Kaufmann Publishers Inc., San Francisco","edition":"5"},{"key":"9423_CR47","volume-title":"Computer architecture. A quantitative approach","author":"JL Hennessy","year":"2017","unstructured":"Hennessy JL, Patterson DA (2017) Computer architecture. A quantitative approach, 6th edn. Morgan Kaufmann Publishers Inc., San Francisco","edition":"6"},{"issue":"2","key":"9423_CR48","doi-asserted-by":"publisher","first-page":"48","DOI":"10.1145\/3282307","volume":"62","author":"JL Hennessy","year":"2019","unstructured":"Hennessy JL, Patterson DA (2019) A new golden age for computer architecture. Commun ACM 62(2):48\u201360","journal-title":"Commun ACM"},{"key":"9423_CR49","unstructured":"Hermant JF, George L (2007) A C-space sensitivity analysis of earliest deadline first scheduling. In: Workshop on Leveraging Applications of Fmethods, Verification and Validation, pp 21\u201333"},{"key":"9423_CR50","unstructured":"Intel (2015) Improving real-time performance by utilizing cache allocation technology. https:\/\/www.intel.com\/content\/dam\/www\/public\/us\/en\/documents\/white-papers\/cache-allocation-technology-white-paper.pdf"},{"issue":"5","key":"9423_CR51","doi-asserted-by":"publisher","first-page":"390","DOI":"10.1093\/comjnl\/29.5.390","volume":"29","author":"M Joseph","year":"1986","unstructured":"Joseph M, Pandya P (1986) Finding response times in a real-time system. Comput J 29(5):390\u2013395","journal-title":"Comput J"},{"key":"9423_CR52","doi-asserted-by":"crossref","unstructured":"Kim H, Kandhalu A, Rajkumar R (2013) A coordinated approach for practical OS-level cache management in multi-core real-time systems. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 80\u201389","DOI":"10.1109\/ECRTS.2013.19"},{"key":"9423_CR53","doi-asserted-by":"crossref","unstructured":"Kirk DB (1989) SMART (strategic memory allocation for real-time) cache design. In: IEEE Real-Time Systems Symposium (RTSS), pp 229\u2013237","DOI":"10.1109\/REAL.1989.63574"},{"key":"9423_CR54","doi-asserted-by":"crossref","unstructured":"Kirk DB, Strosnider JK, Sasinowski JE (1991) Allocating smart cache segments for schedulability. In: Euromicro Workshop on Real-Time Systems, pp 41\u201350","DOI":"10.1109\/EMWRT.1991.144078"},{"key":"9423_CR55","doi-asserted-by":"crossref","unstructured":"Kloda T, Solieri M, Mancuso R, et\u00a0al (2019) Deterministic memory hierarchy and virtualization for modern multi-core embedded systems. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 1\u201314","DOI":"10.1109\/RTAS.2019.00009"},{"issue":"3","key":"9423_CR56","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3587694","volume":"22","author":"T Kloda","year":"2023","unstructured":"Kloda T, Gracioli G, Tabish R et al (2023) Lazy load scheduling for mixed-criticality applications in heterogeneous mpsocs. ACM Trans Embed Comput Syst 22(3):1\u201326","journal-title":"ACM Trans Embed Comput Syst"},{"key":"9423_CR57","doi-asserted-by":"crossref","unstructured":"Kritikakou A, Pagetti C, Baldellon O, et\u00a0al (2014) Run-time control to increase task parallelism in mixed-critical systems. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 119\u2013128","DOI":"10.1109\/ECRTS.2014.14"},{"key":"9423_CR58","doi-asserted-by":"crossref","unstructured":"Kwon O, Schw\u00e4ricke G, Kloda T, et\u00a0al (2021) Flexible cache partitioning for multi-mode real-time systems. In: Design, Automation & Test in Europe Conference & Exhibition (DATE), pp 1156\u20131161","DOI":"10.23919\/DATE51398.2021.9474240"},{"key":"9423_CR59","doi-asserted-by":"crossref","unstructured":"Lesage B, Puaut I, Seznec A (2012) Preti: Partitioned real-time shared cache for mixed-criticality real-time systems. In: International Conference on Real-Time Networks and Systems (RTNS), pp 171\u2013180","DOI":"10.1145\/2392987.2393009"},{"key":"9423_CR60","doi-asserted-by":"crossref","unstructured":"Lesage B, Griffin D, Soboczenski F, et\u00a0al (2015) A framework for the evaluation of measurement-based timing analyses. In: International Conference on Real-Time Networks and Systems (RTNS), pp 35\u201344","DOI":"10.1145\/2834848.2834858"},{"key":"9423_CR61","unstructured":"Limited A (2008) Primecell level 2 cache controller (PL310) technical reference manual. https:\/\/developer.arm.com\/documentation\/ddi0246\/c\/introduction\/about-the-primecell-level-2-cache-controller--pl310-"},{"issue":"1","key":"9423_CR62","doi-asserted-by":"publisher","first-page":"46","DOI":"10.1145\/321738.321743","volume":"20","author":"CL Liu","year":"1973","unstructured":"Liu CL, Layland JW (1973) Scheduling algorithms for multiprogramming in a hard-real-time environment. J ACM 20(1):46\u201361","journal-title":"J ACM"},{"key":"9423_CR63","doi-asserted-by":"crossref","unstructured":"Lunniss W, Altmeyer S, Maiza C, et\u00a0al (2013) Integrating cache related pre-emption delay analysis into EDF scheduling. In: 2013 IEEE 19th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 75\u201384","DOI":"10.1109\/RTAS.2013.6531081"},{"key":"9423_CR64","doi-asserted-by":"crossref","unstructured":"Mancuso R, Dudko R, Betti E, et\u00a0al (2013) Real-time cache management framework for multi-core architectures. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS)","DOI":"10.1109\/RTAS.2013.6531078"},{"key":"9423_CR65","doi-asserted-by":"crossref","unstructured":"Martins J, Pinto S (2023) Shedding light on static partitioning hypervisors for arm-based mixed-criticality systems. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 40\u201353","DOI":"10.1109\/RTAS58335.2023.00011"},{"issue":"7","key":"9423_CR66","doi-asserted-by":"publisher","first-page":"1805","DOI":"10.1109\/TC.2014.2346178","volume":"64","author":"THC Nguyen","year":"2015","unstructured":"Nguyen THC, Richard P, Grolleau E (2015) An fptas for response time analysis of fixed priority real-time tasks with resource augmentation. IEEE Trans Comput 64(7):1805\u20131818","journal-title":"IEEE Trans Comput"},{"key":"9423_CR67","doi-asserted-by":"crossref","unstructured":"Pan X, Mueller F (2018) Controller-aware memory coloring for multicore real-time systems. In: ACM Symposium on Applied Computing, pp 584\u2013592","DOI":"10.1145\/3167132.3167196"},{"key":"9423_CR68","doi-asserted-by":"crossref","unstructured":"Paolieri M, Qui\u00f1ones E, Cazorla FJ, et\u00a0al (2011) IA3: An interference aware allocation algorithm for multicore hard real-time systems. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 280\u2013290","DOI":"10.1109\/RTAS.2011.34"},{"key":"9423_CR69","doi-asserted-by":"crossref","unstructured":"Pellizzoni R, Betti E, Bak S, et\u00a0al (2011) A predictable execution model for COTS-based embedded systems. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 269\u2013279","DOI":"10.1109\/RTAS.2011.33"},{"key":"9423_CR70","unstructured":"Plazar S, Lokuciejewski P, Marwedel P (2009) WCET-aware software based cache partitioning for multi-task real-time systems. In: International Workshop on Worst-Case Execution Time Analysis, pp 1\u201311"},{"issue":"6","key":"9423_CR71","first-page":"205","volume":"29","author":"I Ripoll","year":"1996","unstructured":"Ripoll I, Crespo A, Mok A et al (1996) Improvement in feasibility testing for real-time tasks1. IFAC 29(6):205\u2013212","journal-title":"IFAC"},{"issue":"8","key":"9423_CR72","doi-asserted-by":"publisher","first-page":"997","DOI":"10.1109\/12.238493","volume":"42","author":"JE Sasinowski","year":"1993","unstructured":"Sasinowski JE, Strosnider JK (1993) A dynamic programming algorithm for cache memory partitioning for real-time systems. IEEE Trans Comput 42(8):997\u20131001","journal-title":"IEEE Trans Comput"},{"key":"9423_CR73","volume-title":"Valgrind 3.3 - Advanced debugging and profiling for GNU\/Linux applications","author":"J Seward","year":"2008","unstructured":"Seward J, Nethercote N, Weidendorfer J (2008) Valgrind 3.3 - Advanced debugging and profiling for GNU\/Linux applications. Network Theory Ltd, Godalming"},{"key":"9423_CR74","doi-asserted-by":"crossref","unstructured":"Shen Y, Xiao J, Pimentel AD (2022) TCPS: a task and cache-aware partitioned scheduler for hard real-time multi-core systems. In: ACM International Conference on Languages, Compilers, and Tools for Embedded Systems, pp 37\u201349","DOI":"10.1145\/3519941.3535067"},{"key":"9423_CR75","doi-asserted-by":"publisher","DOI":"10.1007\/s11241-023-09408-y","author":"A Singh","year":"2023","unstructured":"Singh A (2023) Cutting-plane algorithms for preemptive uniprocessor scheduling problems. Real-Time Syst. https:\/\/doi.org\/10.1007\/s11241-023-09408-y","journal-title":"Real-Time Syst"},{"issue":"3","key":"9423_CR76","doi-asserted-by":"publisher","first-page":"135","DOI":"10.1145\/1353536.1346299","volume":"43","author":"S Srikantaiah","year":"2008","unstructured":"Srikantaiah S, Kandemir M, Irwin MJ (2008) Adaptive set pinning: managing shared caches in chip multiprocessors. ACM Sigplan Notices 43(3):135\u2013144","journal-title":"ACM Sigplan Notices"},{"key":"9423_CR77","doi-asserted-by":"crossref","unstructured":"Sun B, Kloda T, Arribas\u00a0Garcia S, et\u00a0al (2023a) Minimizing cache usage for real-time systems. In: International Conference on Real-Time Networks and Systems (RTNS), pp 200\u2013211","DOI":"10.1145\/3575757.3593651"},{"key":"9423_CR78","doi-asserted-by":"crossref","unstructured":"Sun B, Roy D, Kloda T, et\u00a0al (2023b) Co-optimizing cache partitioning and multi-core task scheduling: Exploit cache sensitivity or not? In: IEEE Real-Time Systems Symposium (RTSS)","DOI":"10.1109\/RTSS59052.2023.00028"},{"key":"9423_CR79","doi-asserted-by":"crossref","unstructured":"Suzuki N, Kim H, Niz Dd, et\u00a0al (2013) Coordinated bank and cache coloring for temporal protection of memory accesses. In: IEEE International Conference on Computational Science and Engineering, pp 685\u2013692","DOI":"10.1109\/CSE.2013.106"},{"key":"9423_CR80","doi-asserted-by":"crossref","unstructured":"Thomas S, Gohkale C, Tanuwidjaja E, et\u00a0al (2014) CortexSuite: a synthetic brain benchmark suite. In: International Symposium on Workload Characterization","DOI":"10.1109\/IISWC.2014.6983043"},{"key":"9423_CR81","doi-asserted-by":"crossref","unstructured":"Tomiyama H, Dutt N (2000) Program path analysis to bound cache-related preemption delay in preemptive real-time systems. In: International Workshop on Hardware\/Software Codesign, pp 67\u201371","DOI":"10.1145\/334012.334025"},{"key":"9423_CR82","doi-asserted-by":"crossref","unstructured":"Wang W, Mishra P, Ranka S (2011) Dynamic cache reconfiguration and partitioning for energy optimization in real-time multi-core systems. In: ACM\/IEEE Design Automation Conference (DAC), pp 948\u2013953","DOI":"10.1145\/2024724.2024935"},{"key":"9423_CR83","doi-asserted-by":"crossref","unstructured":"Ward BC, Herman JL, Kenna CJ, et\u00a0al (2013) Making shared caches more predictable on multicore platforms. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 157\u2013167","DOI":"10.1109\/ECRTS.2013.26"},{"issue":"10","key":"9423_CR84","doi-asserted-by":"publisher","first-page":"1487","DOI":"10.1109\/TC.2020.2974224","volume":"69","author":"J Xiao","year":"2020","unstructured":"Xiao J, Altmeyer S, Pimentel AD (2020) Schedulability analysis of global scheduling for multicore systems with shared caches. IEEE Trans Comput 69(10):1487\u20131499","journal-title":"IEEE Trans Comput"},{"issue":"3","key":"9423_CR85","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/3487581","volume":"21","author":"J Xiao","year":"2022","unstructured":"Xiao J, Shen Y, Pimentel AD (2022) Cache interference-aware task partitioning for non-preemptive real-time multi-core systems. ACM Trans Embed Comput Syst 21(3):1\u201328","journal-title":"ACM Trans Embed Comput Syst"},{"key":"9423_CR86","doi-asserted-by":"crossref","unstructured":"Xu M, Phan LTX, Choi HY, et\u00a0al (2019) Holistic resource allocation for multicore real-time systems. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 345\u2013356","DOI":"10.1109\/RTAS.2019.00036"},{"key":"9423_CR87","doi-asserted-by":"crossref","unstructured":"Yang S, Powell M, Falsafi B, et\u00a0al (2001) An integrated circuit\/architecture approach to reducing leakage in deep-submicron high-performance i-caches. In: International Symposium on High-Performance Computer Architecture, pp 147\u2013157","DOI":"10.1109\/HPCA.2001.903259"},{"key":"9423_CR88","doi-asserted-by":"crossref","unstructured":"Yang SH, Powell M, Falsafi B, et\u00a0al (2002) Exploiting choice in resizable cache design to optimize deep-submicron processor energy-delay. In: International Symposium on High Performance Computer Architecture, pp 151\u2013161","DOI":"10.1109\/HPCA.2002.995706"},{"key":"9423_CR89","doi-asserted-by":"crossref","unstructured":"Ye Y, West R, Cheng Z, et\u00a0al (2014) COLORIS: A dynamic cache partitioning system using page coloring. In: International Conference on Parallel Architecture and Compilation Techniques, pp 381\u2013392","DOI":"10.1145\/2628071.2628104"},{"key":"9423_CR90","unstructured":"Yun H, Yao G, Pellizzoni R, et\u00a0al (2013) Memguard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 55\u201364"},{"key":"9423_CR91","doi-asserted-by":"crossref","unstructured":"Yun H, Mancuso R, Wu ZP, et\u00a0al (2014) Palloc: Dram bank-aware memory allocator for performance isolation on multicore platforms. In: IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 155\u2013166","DOI":"10.1109\/RTAS.2014.6925999"},{"key":"9423_CR92","doi-asserted-by":"crossref","unstructured":"Zhang C, Vahid F, Najjar W (2003) A highly configurable cache architecture for embedded systems. In: International Symposium on Computer Architecture (ISCA), pp 136\u2013146","DOI":"10.1109\/ISCA.2003.1206995"},{"key":"9423_CR93","doi-asserted-by":"crossref","unstructured":"Zhang F, Burns A (2009) Improvement to quick processor-demand analysis for EDF-scheduled real-time systems. In: Euromicro Conference on Real-Time Systems (ECRTS), pp 76\u201386","DOI":"10.1109\/ECRTS.2009.20"},{"issue":"3","key":"9423_CR94","first-page":"1","volume":"12","author":"F Zhang","year":"2013","unstructured":"Zhang F, Burns A (2013) Schedulability analysis of EDF-scheduled embedded real-time systems with resource sharing. ACM Trans Embed Comput Syst 12(3):1\u20139","journal-title":"ACM Trans Embed Comput Syst"},{"issue":"10","key":"9423_CR95","doi-asserted-by":"publisher","first-page":"2333","DOI":"10.1109\/TCAD.2019.2937807","volume":"39","author":"W Zhang","year":"2020","unstructured":"Zhang W, Guan N, Ju L et al (2020) Scope-aware useful cache block calculation for cache-related pre-emption delay analysis with set-associative data caches. IEEE Trans Comput-Aided Design Integr Circ Syst 39(10):2333\u20132346","journal-title":"IEEE Trans Comput-Aided Design Integr Circ Syst"},{"key":"9423_CR96","doi-asserted-by":"crossref","unstructured":"Zhang Y, Guo Z, Wang L, et\u00a0al (2017) Integrating cache-related preemption delay into GEDF analysis for multiprocessor scheduling with on-chip cache. In: IEEE Trustcom\/BigDataSE\/ICESS, pp 815\u2013822","DOI":"10.1109\/Trustcom\/BigDataSE\/ICESS.2017.317"},{"key":"9423_CR97","doi-asserted-by":"crossref","unstructured":"Zhang Z, Shen Y, Sun B, et\u00a0al (2022) Memory allocation for low-power real-time embedded microcontroller: a case study. In: IEEE International Conference on Emerging Technologies and Factory Automation (ETFA), pp 1\u20134","DOI":"10.1109\/ETFA52439.2022.9921611"},{"key":"9423_CR98","doi-asserted-by":"crossref","unstructured":"Zuepke A, Bastoni A, Chen W, et\u00a0al (2023) Mempol: Policing core memory bandwidth from outside of the cores. In: 2023 IEEE 29th Real-Time and Embedded Technology and Applications Symposium (RTAS), pp 235\u2013248","DOI":"10.1109\/RTAS58335.2023.00026"}],"container-title":["Real-Time Systems"],"original-title":[],"language":"en","link":[{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-024-09423-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/article\/10.1007\/s11241-024-09423-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"https:\/\/link.springer.com\/content\/pdf\/10.1007\/s11241-024-09423-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,12]],"date-time":"2024-12-12T15:06:30Z","timestamp":1734015990000},"score":1,"resource":{"primary":{"URL":"https:\/\/link.springer.com\/10.1007\/s11241-024-09423-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,6,28]]},"references-count":98,"journal-issue":{"issue":"4","published-print":{"date-parts":[[2024,12]]}},"alternative-id":["9423"],"URL":"https:\/\/doi.org\/10.1007\/s11241-024-09423-7","relation":{},"ISSN":["0922-6443","1573-1383"],"issn-type":[{"type":"print","value":"0922-6443"},{"type":"electronic","value":"1573-1383"}],"subject":[],"published":{"date-parts":[[2024,6,28]]},"assertion":[{"value":"24 May 2024","order":1,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"28 June 2024","order":2,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}},{"order":1,"name":"Ethics","group":{"name":"EthicsHeading","label":"Declarations"}},{"value":"The authors have not disclosed any competing interests.","order":2,"name":"Ethics","group":{"name":"EthicsHeading","label":"Competing interests"}}]}}