{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:51:40Z","timestamp":1761580300041,"version":"3.32.0"},"reference-count":41,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2005,6,1]],"date-time":"2005-06-01T00:00:00Z","timestamp":1117584000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2005,6]]},"DOI":"10.1007\/s11265-005-4962-2","type":"journal-article","created":{"date-parts":[[2005,3,31]],"date-time":"2005-03-31T12:43:42Z","timestamp":1112273022000},"page":"215-237","source":"Crossref","is-referenced-by-count":13,"title":["On Design of Parallel Memory Access Schemes for Video Coding"],"prefix":"10.1007","volume":"40","author":[{"given":"Jarno K.","family":"Tanskanen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Reiner","family":"Creutzburg","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jarkko T.","family":"Niittylahti","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2005,6,1]]},"reference":[{"key":"4962_CR1","doi-asserted-by":"crossref","unstructured":"J. Kneip, K. R\u00f6nner, and P. Pirsch, \u201cA Data Path Array with Shared Memory as Core of a High Performance DSP,\u201d in Proc. Int. Conf. Applicat. Specific Array Processors \u201894, San Francisco, CA, U.S.A., Aug. 22\u201324, 1994, pp. 271\u2013282.","DOI":"10.1109\/ASAP.1994.331797"},{"issue":"1","key":"4962_CR2","doi-asserted-by":"crossref","first-page":"56","DOI":"10.1109\/76.486420","volume":"6","author":"K. R\u00f6nner","year":"1996","unstructured":"K. R\u00f6nner and J. Kneip, \u201cArchitecture and Applications of the HiPAR Video Signal Processor,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 6, no. 1, 1996, pp. 56\u201366.","journal-title":"IEEE Trans. Circuits Syst. Video Technol."},{"issue":"7","key":"4962_CR3","doi-asserted-by":"crossref","first-page":"946","DOI":"10.1109\/4.848202","volume":"35","author":"W. Hinrichs","year":"2000","unstructured":"W. Hinrichs, J.P. Wittenburg, H. Lieske, H. Kloos, M. Ohmacht, and P. Pirsch, \u201cA 1.3-GOPS Parallel DSP for High-Performance Image-Processing Applications,\u201d IEEE Journal of Solid-State Circuits, vol. 35, no. 7, 2000, pp. 946\u2013952.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"4962_CR4","unstructured":"Y.H. Hu (Ed.), Programmable Digital Signal Processors: Architecture, Programming, and Applications, Marcel Dekker, Inc., New York, NY, U.S.A., 2002."},{"key":"4962_CR5","unstructured":"Texas Instruments, Inc., TMS320C6000 CPU and Instruction Set Reference Guide, Oct. 2000."},{"issue":"4","key":"4962_CR6","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/40.526925","volume":"16","author":"R.B. Lee","year":"1996","unstructured":"R.B. Lee, \u201cSubword Parallelism with MAX-2,\u201d IEEE Micro, vol. 16, no. 4, 1996, pp. 51\u201359.","journal-title":"IEEE Micro"},{"issue":"12","key":"4962_CR7","doi-asserted-by":"crossref","first-page":"1566","DOI":"10.1109\/T-C.1971.223171","volume":"C-20","author":"P. Budnik","year":"1971","unstructured":"P. Budnik and D.J. Kuck, \u201cThe Organization and Use of Parallel Memories,\u201d IEEE Trans. Computers, vol. C-20, no. 12, 1971, pp. 1566\u20131569.","journal-title":"IEEE Trans. Computers"},{"issue":"12","key":"4962_CR8","doi-asserted-by":"crossref","first-page":"1145","DOI":"10.1109\/T-C.1975.224157","volume":"C-24","author":"D.H. Lawrie","year":"1975","unstructured":"D.H. Lawrie, \u201cAccess and Alignment of Data in an Array Processor,\u201d IEEE Trans. Computers, vol. C-24, no. 12, 1975, pp. 1145\u20131155.","journal-title":"IEEE Trans. Computers"},{"issue":"8","key":"4962_CR9","doi-asserted-by":"crossref","first-page":"758","DOI":"10.1109\/TC.1968.229159","volume":"C-17","author":"D.J. Kuck","year":"1968","unstructured":"D.J. Kuck, \u201cILLIAC IV Software and Application Programming,\u201d IEEE Trans. Computers, vol. C-17, no. 8, 1968, pp. 758\u2013770.","journal-title":"IEEE Trans. Computers"},{"issue":"2","key":"4962_CR10","doi-asserted-by":"crossref","first-page":"174","DOI":"10.1109\/TC.1977.5009297","volume":"C-26","author":"K.E. Batcher","year":"1977","unstructured":"K.E. Batcher, \u201cThe Multidimensional Access Memory in STARAN,\u201d IEEE Trans. Computers, vol. C-26, no. 2, 1977, pp. 174\u2013177.","journal-title":"IEEE Trans. Computers"},{"issue":"5","key":"4962_CR11","doi-asserted-by":"crossref","first-page":"363","DOI":"10.1109\/TC.1982.1676014","volume":"C-31","author":"D.J. Kuck","year":"1982","unstructured":"D.J. Kuck and R.A. Stokes, \u201cThe Burroughs Scientific Processor (BSP),\u201d IEEE Trans. Computers, vol. C-31, no. 5, 1982, pp. 363\u2013376.","journal-title":"IEEE Trans. Computers"},{"issue":"2","key":"4962_CR12","doi-asserted-by":"crossref","first-page":"113","DOI":"10.1109\/TC.1978.1675045","volume":"C-27","author":"D.C. Van Voorhis","year":"1978","unstructured":"D.C. Van Voorhis and T.H. Morrin, \u201cMemory Systems for Image Processing,\u201d IEEE Trans. Computers, vol. C-27, no. 2, 1978, pp. 113\u2013125.","journal-title":"IEEE Trans. Computers"},{"issue":"7","key":"4962_CR13","doi-asserted-by":"crossref","first-page":"669","DOI":"10.1109\/TC.1986.1676813","volume":"C-35","author":"J.W. Park","year":"1986","unstructured":"J.W. Park, \u201cAn Efficient Memory System for Image Processing,\u201d IEEE Trans. Computers, vol. C-35, no. 7, 1986, pp. 669-674.","journal-title":"IEEE Trans. Computers"},{"issue":"1","key":"4962_CR14","doi-asserted-by":"crossref","first-page":"32","DOI":"10.1145\/357314.357316","volume":"2","author":"R.F. Sproull","year":"1983","unstructured":"R.F. Sproull, I.E. Sutherland, A. Thompson, S. Gupta, and C. Minter, \u201cThe 8 by 8 Display,\u201d ACM Trans. Graphics, vol. 2, no. 1, 1983, pp. 32\u201356.","journal-title":"ACM Trans. Graphics"},{"issue":"5","key":"4962_CR15","doi-asserted-by":"crossref","first-page":"707","DOI":"10.1109\/12.381958","volume":"44","author":"D. Cohen-Or","year":"1995","unstructured":"D. Cohen-Or and A. Kaufman, \u201cA 3D Skewing and De-Skewing Scheme for Conflict-Free Access to Rays in Volume Rendering,\u201d IEEE Trans. Computers, vol. 44, no. 5, 1995, pp. 707\u2013710.","journal-title":"IEEE Trans. Computers"},{"issue":"1","key":"4962_CR16","doi-asserted-by":"crossref","first-page":"34","DOI":"10.1109\/12.192212","volume":"42","author":"G.S. Sohi","year":"1993","unstructured":"G.S. Sohi, \u201cHigh-Bandwidth Interleaved Memories for Vector Processors\u2014A Simulation Study,\u201d IEEE Trans. Computers, vol. 42, no. 1, 1993, pp. 34\u201344.","journal-title":"IEEE Trans. Computers"},{"key":"4962_CR17","volume-title":"Memory Architecture & Parallel Access","author":"M. G\u00f6ssel","year":"1994","unstructured":"M. G\u00f6ssel, B. Rebel, and R. Creutzburg, Memory Architecture & Parallel Access, Elsevier Science, Ltd., Amsterdam, The Netherlands, 1994."},{"issue":"6","key":"4962_CR18","doi-asserted-by":"crossref","first-page":"57","DOI":"10.1109\/MC.1979.1658780","volume":"12","author":"H.J. Siegel","year":"1979","unstructured":"H.J. Siegel, \u201cInterconnection Networks for SIMD Machines,\u201d Computer, vol. 12, no. 6, 1979, pp. 57\u201365.","journal-title":"Computer"},{"issue":"6","key":"4962_CR19","doi-asserted-by":"crossref","first-page":"595","DOI":"10.1109\/71.506698","volume":"7","author":"A. Deb","year":"1996","unstructured":"A. Deb, \u201cMultiskewing\u2014A Novel Technique for Optimal Parallel Memory Access,\u201d IEEE Trans. Parallel and Distrib. Syst., vol. 7, no. 6, 1996, pp. 595\u2013604.","journal-title":"IEEE Trans. Parallel and Distrib. Syst."},{"issue":"2","key":"4962_CR20","doi-asserted-by":"crossref","first-page":"162","DOI":"10.1006\/jpdc.1995.1038","volume":"25","author":"Z. Liu","year":"1995","unstructured":"Z. Liu and X. Li, \u201cXOR Storage Schemes for Frequently Used Data Patterns,\u201d Journal of Parallel and Distributed Computing, vol. 25, no. 2, 1995, pp. 162\u2013173.","journal-title":"Journal of Parallel and Distributed Computing"},{"issue":"6","key":"4962_CR21","doi-asserted-by":"crossref","first-page":"757","DOI":"10.1109\/12.506432","volume":"45","author":"M.A. Al-Mouhamed","year":"1996","unstructured":"M.A. Al-Mouhamed and S.S. Seiden, \u201cMinimization of Memory and Network Contention for Accessing Arbitrary Data Patterns in SIMD Systems,\u201d IEEE Trans. Computers, vol. 45, no. 6, 1996, pp. 757\u2013762.","journal-title":"IEEE Trans. Computers"},{"key":"4962_CR22","unstructured":"J.M. Frailong, W. Jalby, and J. Lenfant, \u201cXOR-Schemes: A Flexible Data Organization in Parallel Memories,\u201d in Proc. Int. Conf. Parallel Processing, St. Charles, IL, U.S.A., Aug. 20\u201323, 1985, pp. 276\u2013283."},{"issue":"4","key":"4962_CR23","doi-asserted-by":"crossref","first-page":"361","DOI":"10.1109\/71.219753","volume":"4","author":"K. Kim","year":"1993","unstructured":"K. Kim and V.K. Prasanna, \u201cLatin Squares for Parallel Array Access,\u201d IEEE Trans. Parallel and Distrib. Syst., vol. 4, no. 4, 1993, pp. 361\u2013370.","journal-title":"IEEE Trans. Parallel and Distrib. Syst."},{"issue":"3","key":"4962_CR24","doi-asserted-by":"crossref","first-page":"111","DOI":"10.1016\/0020-0190(90)90078-C","volume":"36","author":"D.-L. Lee","year":"1990","unstructured":"D.-L. Lee, \u201cEfficient Address Generation in a Parallel Processor,\u201d Information Processing Letters, vol. 36, no. 3, 1990, pp. 111\u2013116.","journal-title":"Information Processing Letters"},{"issue":"1","key":"4962_CR25","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1016\/0020-0190(89)90180-4","volume":"33","author":"D.-L. Lee","year":"1989","unstructured":"D.-L. Lee, \u201cOn Access and Alignment of Data in a Parallel Processor,\u201d Information Processing Letters, vol. 33, no. 1, 1989, pp. 11\u201314.","journal-title":"Information Processing Letters"},{"issue":"4","key":"4962_CR26","doi-asserted-by":"crossref","first-page":"499","DOI":"10.1109\/12.135554","volume":"41","author":"D.-L. Lee","year":"1992","unstructured":"D.-L. Lee, \u201cArchitecture of an Array Processor Using a Nonlinear Skewing Scheme,\u201d IEEE Trans. Computers, vol. 41, no. 4, 1992, pp. 499\u2013505.","journal-title":"IEEE Trans. Computers"},{"issue":"2","key":"4962_CR27","doi-asserted-by":"crossref","first-page":"233","DOI":"10.1109\/TC.1987.1676887","volume":"C-36","author":"H.A.G. Wijshoff","year":"1987","unstructured":"H.A.G. Wijshoff and J. van Leeuwen, \u201cOn Linear Skewing Schemes and d-Ordered Vectors,\u201d IEEE Trans. Computers, vol. C-36, no. 2, 1987, pp. 233\u2013239.","journal-title":"IEEE Trans. Computers"},{"key":"4962_CR28","doi-asserted-by":"crossref","unstructured":"K. Kim and V.K. Prasanna Kumar, \u201cPerfect Latin Squares and Parallel Array Access,\u201d in Proc. 16th Ann. Int. Symp. Computer Architecture, Jerusalem, Israel, May 28\u2013June 1, 1989, pp. 372\u2013379.","DOI":"10.1145\/74925.74967"},{"key":"4962_CR29","unstructured":"W. Jalby, J.M. Frailong, and J. Lenfant, \u201cDiamond Schemes: An Organization of Parallel Memories for Efficient Array Processing,\u201d Rapports de Recherche, No. 342, INRIA, Centre de Rocquencourt, France, Oct. 1984."},{"issue":"5","key":"4962_CR30","doi-asserted-by":"crossref","first-page":"421","DOI":"10.1109\/TC.1978.1675122","volume":"C-27","author":"H.D. Shapiro","year":"1978","unstructured":"H.D. Shapiro, \u201cTheoretical Limitations on the Efficient Use of Parallel Memories,\u201d IEEE Trans. Computers, vol. C-27, no. 5, 1978, pp. 421\u2013428.","journal-title":"IEEE Trans. Computers"},{"issue":"5","key":"4962_CR31","doi-asserted-by":"crossref","first-page":"435","DOI":"10.1109\/TC.1982.1676020","volume":"C-31","author":"D.H. Lawrie","year":"1982","unstructured":"D.H. Lawrie and C.R. Vora, \u201cThe Prime Memory System for Array Access,\u201d IEEE Trans. Computers, vol. C-31, no. 5, 1982, pp. 435\u2013442.","journal-title":"IEEE Trans. Computers"},{"key":"4962_CR32","unstructured":"A. Norton and E. Melton, \u201cA Class of Boolean Linear Transformations for Conflict-Free Power-of-Two Stride Access,\u201d in Proc. Int. Conf. Parallel Processing, Pennsylvania State Univ., University Park, PA, U.S.A., Aug. 17\u201321, 1987, pp. 247\u2013254."},{"issue":"1","key":"4962_CR33","doi-asserted-by":"crossref","first-page":"43","DOI":"10.1109\/71.80188","volume":"2","author":"D.T. Harper III","year":"1991","unstructured":"D.T. Harper III, \u201cBlock, Multistride Vector, and FFT Accesses in Parallel Memory Systems,\u201d IEEE Trans. Parallel and Distrib. Syst., vol. 2, no. 1, 1991, pp. 43\u201351.","journal-title":"IEEE Trans. Parallel and Distrib. Syst."},{"issue":"6","key":"4962_CR34","doi-asserted-by":"crossref","first-page":"501","DOI":"10.1109\/TC.1985.5009402","volume":"C-34","author":"H.A.G. Wijshoff","year":"1985","unstructured":"H.A.G. Wijshoff and J. van Leeuwen, \u201cThe Structure of Periodic Storage Schemes for Parallel Memories,\u201d IEEE Trans. Computers, vol. C-34, no. 6, 1985, pp. 501\u2013505.","journal-title":"IEEE Trans. Computers"},{"issue":"2","key":"4962_CR35","doi-asserted-by":"crossref","first-page":"355","DOI":"10.1016\/0743-7315(89)90025-7","volume":"7","author":"G. Tel","year":"1989","unstructured":"G. Tel and H.A.G. Wijshoff, \u201cHierarchical Parallel Memory Systems and Multiperiodic Skewing Schemes,\u201d Journal of Parallel and Distributed Computing, vol. 7, no. 2, 1989, pp. 355\u2013367.","journal-title":"Journal of Parallel and Distributed Computing"},{"key":"4962_CR36","doi-asserted-by":"crossref","unstructured":"S. Chen, A. Postula, and L. Jozwiak, \u201cSynthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention,\u201d in Proc. 25th EUROMICRO Conference, Milan, Italy, Sept. 8\u201310, 1999, vol. 1, pp. 170\u2013177.","DOI":"10.1109\/EURMIC.1999.794463"},{"issue":"2","key":"4962_CR37","doi-asserted-by":"crossref","first-page":"173","DOI":"10.1023\/B:VLSI.0000040428.04740.fe","volume":"38","author":"J.K. Tanskanen","year":"2004","unstructured":"J.K. Tanskanen and J.T. Niittylahti, \u201cScalable Parallel Memory Architectures for Video Coding,\u201d Journal of VLSI Signal Processing, vol. 38, no. 2, 2004, pp. 173\u2013199.","journal-title":"Journal of VLSI Signal Processing"},{"key":"4962_CR38","doi-asserted-by":"crossref","first-page":"201","DOI":"10.1007\/3-540-51815-0_54","volume-title":"Recent Issues in Pattern Analysis and Recognition, Lecture Notes in Comp. Science, vol. 399","author":"M. G\u00f6ssel","year":"1989","unstructured":"M. G\u00f6ssel and B. Rebel, \u201cParallel Access to Rectangles,\u201d in: V. Cantoni, R. Creutzburg, S. Levialdi, G. Wolf (Eds.), Recent Issues in Pattern Analysis and Recognition, Lecture Notes in Comp. Science, vol. 399, pp. 201\u2013213, Springer-Verlag, Berlin, Germany, 1989."},{"key":"4962_CR39","doi-asserted-by":"crossref","unstructured":"J. Tanskanen, T. Sihvo, J. Niittylahti, J. Takala, and R. Creutzburg, \u201cParallel Memory Access Schemes for H.263 Encoder,\u201d in Proc. IEEE Int. Symp. Circuits and Systems, Geneva, Switzerland, May 28\u201331 2000, vol. 1, pp. 691\u2013694.","DOI":"10.1109\/ISCAS.2000.857189"},{"key":"4962_CR40","doi-asserted-by":"crossref","unstructured":"S. Dutta, K.J. O\u2019Connor, and A. Wolfe, \u201cHigh-Performance Crossbar Interconnect for a VLIW Video Signal Processor,\u201d in Proc. Ninth Ann. IEEE Int. ASIC Conference and Exhibit, Rochester, NY, U.S.A., Sept. 23\u201327, 1996, pp. 45\u201349.","DOI":"10.1109\/ASIC.1996.551961"},{"issue":"4","key":"4962_CR41","doi-asserted-by":"crossref","first-page":"501","DOI":"10.1109\/76.709414","volume":"8","author":"S. Dutta","year":"1998","unstructured":"S. Dutta, K.J. O\u2019Connor, W. Wolf, and A. Wolfe, \u201cA Design Study of a 0.25-\u03bc m Video Signal Processor,\u201d IEEE Trans. Circuits Syst. Video Technol., vol. 8, no. 4, 1998, pp. 501\u2013519.","journal-title":"IEEE Trans. Circuits Syst. Video Technol"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-005-4962-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-005-4962-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-005-4962-2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,29]],"date-time":"2024-12-29T18:49:15Z","timestamp":1735498155000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-005-4962-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2005,6]]},"references-count":41,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2005,6]]}},"alternative-id":["4962"],"URL":"https:\/\/doi.org\/10.1007\/s11265-005-4962-2","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[2005,6]]}}}