{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,9]],"date-time":"2025-01-09T03:10:01Z","timestamp":1736392201883,"version":"3.32.0"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"2-3","license":[{"start":{"date-parts":[[2006,6,1]],"date-time":"2006-06-01T00:00:00Z","timestamp":1149120000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2006,6]]},"DOI":"10.1007\/s11265-006-7271-5","type":"journal-article","created":{"date-parts":[[2006,5,29]],"date-time":"2006-05-29T22:28:46Z","timestamp":1148941726000},"page":"207-221","source":"Crossref","is-referenced-by-count":12,"title":["Multidimensional DSP Core Synthesis for FPGA"],"prefix":"10.1007","volume":"43","author":[{"given":"J.","family":"Mcallister","sequence":"first","affiliation":[]},{"given":"R.","family":"Woods","sequence":"additional","affiliation":[]},{"given":"R","family":"Walke","sequence":"additional","affiliation":[]},{"given":"D.","family":"Reilly","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2006,6,1]]},"reference":[{"key":"7271_CR1","volume-title":"Embedded Multiprocessors Scheduling and Synchronization","author":"S. Sriram","year":"2000","unstructured":"S. Sriram and S. S. Bhattacharyya, Embedded Multiprocessors Scheduling and Synchronization, Marcel Dekker, Inc., New York, Basel, 2000."},{"key":"7271_CR2","doi-asserted-by":"crossref","first-page":"580","DOI":"10.1155\/S1110865703212129","volume":"6","author":"B. K. Madahar","year":"2003","unstructured":"B. K. Madahar, et al., \u201cHow Rapid is Rapid Prototyping? Analysis of ESPADON Programme Results,\u201d EURASIP Journal on Applied Signal Processing, vol. 6, 2003, pp. 580\u2013593.","journal-title":"EURASIP Journal on Applied Signal Processing"},{"key":"7271_CR3","doi-asserted-by":"crossref","unstructured":"J. McAllister, R. Woods, R. Walke, and D. Reilly, \u201cSynthesis and High Level Optimisation of Multidimensional Dataflow Actor Networks on FPGA,\u201d in Proc. IEEE W\/shop on Sig. Proc. Sys., Texas, USA, 2004, pp. 164\u2013169.","DOI":"10.1109\/SIPS.2004.1363043"},{"key":"7271_CR4","doi-asserted-by":"crossref","unstructured":"R. Lauwereins, M. Engels, M. Ad\u00e9 and J. A. Peperstraete, \u201cGrape-II: A System-Level Prototyping Environment for DSP Applications,\u201d IEEE Computer, Computer, 1995, pp. 35\u201343.","DOI":"10.1109\/2.347998"},{"key":"7271_CR5","unstructured":"C. Hylands et al., \u201cOverview of the Ptolemy Project,\u201d Technical Memorandum UCB\/ERL M03\/25, University of California at Berkeley, 2003."},{"key":"7271_CR6","unstructured":"The CAP Laboratory of Seoul National University, \u201cPeace Users Manualv.1.0b,\u201d (available from http:\/\/peace.snu.ac.kr ), 25, 2004."},{"key":"7271_CR7","doi-asserted-by":"crossref","unstructured":"T. Stefanov et al., \u201cSystem Design using Kahn Process Networks: The Compaan\/Laura Approach,\u201d Proc. Design Automation and Test in Europe (DATE) Conference, vol.1, Paris, 2004 pp. 340\u2013345.","DOI":"10.1109\/DATE.2004.1268870"},{"key":"7271_CR8","doi-asserted-by":"crossref","unstructured":"E. A. Lee and T. M. Parks, \u201cDataflow Process Networks,\u201d Proc. IEEE, vol. 83, no. 5, 1995, pp. 773\u2013799.","DOI":"10.1109\/5.381846"},{"key":"7271_CR9","doi-asserted-by":"crossref","unstructured":"S. S. Bhattacharyya, P. K. Murthy and E. A. Lee, Software Synthesis from Dataflow Graphs, Kluwer Academic Publishers, 1996.","DOI":"10.1007\/978-1-4613-1389-2"},{"key":"7271_CR10","doi-asserted-by":"crossref","unstructured":"E. A. Lee and D. G. Messerschmitt, \u201cSynchronous Data Flow,\u201d Proc. IEEE, vol. 75, no. 9, 1987, pp. 1235\u20131245.","DOI":"10.1109\/PROC.1987.13876"},{"key":"7271_CR11","doi-asserted-by":"crossref","unstructured":"E. A. Lee, \u201cConsistency in Dataflow Graphs,\u201d IEEE Trans. Parallel and Distributed Systems, vol. 2, no. 2, 1991, pp. 223\u2013235.","DOI":"10.1109\/71.89067"},{"key":"7271_CR12","doi-asserted-by":"crossref","unstructured":"P. K. Murthy and E. A. Lee, \u201cMultidimensional Synchronous Dataflow,\u201d IEEE Trans. Signal Processing, vol. 50, no. 8, 2002, pp. 2064\u20132079.","DOI":"10.1109\/TSP.2002.800830"},{"key":"7271_CR13","first-page":"1340","volume":"2","author":"M. C. Williamson","year":"1996","unstructured":"M. C. Williamson and E. A. Lee, \u201cSynthesis of Parallel Hardware Implementations from Synchronous Dataflow Graph Specifications,\u201d in Proc. 30th Asilomar Conference on Systems, Signals and Computers, vol. 2, USA, 1996, pp. 1340\u2013 1343.","journal-title":"Proc. 30th Asilomar Conference on Systems, Signals and Computers"},{"key":"7271_CR14","doi-asserted-by":"crossref","unstructured":"J. Dalcolmo, R. Lauwereins and M. Ad\u00e9, \u201cCode Generation of Data Dominated DSP Applications for FPGA Targets,\u201d in Proc. 9th International Workshop on Rapid System Prototyping, Belgium, 1998 pp. 162\u2013167.","DOI":"10.1109\/IWRSP.1998.676686"},{"key":"7271_CR15","doi-asserted-by":"crossref","unstructured":"H. Jung and S. Ha, \u201cHardware Synthesis from Coarse-Grained Dataflow Specification for Fast HW\/SW Cosynthesis,\u201d in Proc. International Conference on Hardware\/Software Codesign and System Synthesis Sweden, 2004, pp. 24\u201329.","DOI":"10.1145\/1016720.1016730"},{"key":"7271_CR16","doi-asserted-by":"crossref","unstructured":"T. Harriss, R. Walke, B. Kienhuis and E. F. Deprettere, \u201cCompilation from Matlab to Process Networks Realised in FPGA,\u201d Design Automation for Embedded Systems, vol. 7, no. 4, 2002, pp. 385\u2013403.","DOI":"10.1023\/A:1020367508848"},{"key":"7271_CR17","unstructured":"K. K. Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiley & Sons, Inc., 1999."},{"key":"7271_CR18","doi-asserted-by":"crossref","unstructured":"Y. Yi, R. Woods, L. K. Ting and C. F. N. Cowan, \u201cHigh Speed FPGA-based Implementations of Delayed-LMS Filters,\u201d Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 39, nos. 1\u20132, 2005, pp. 113\u2013 131.","DOI":"10.1023\/B:VLSI.0000047275.54691.be"},{"key":"7271_CR19","unstructured":"Xilinx Inc., Virtex-II ProTM Platform FPGA Handbook, 2002."},{"key":"7271_CR20","unstructured":"D. J. Kaplan and R. S. Stevens, \u201cProcessing Graph Method 2.1 Semantics,\u201d available at http:\/\/www.ait.nrl.navy.mil\/pgmt_home.html , 29, 2002."},{"key":"7271_CR21","doi-asserted-by":"crossref","unstructured":"G. Bilsen, M. Engels, R. Lauwereins and J. Peperstraete, \u201cCyclo-Static Dataflow,\u201d IEEE. Trans. Signal Processing, vol. 44, no. 2, 1996, pp. 397\u2013408.","DOI":"10.1109\/78.485935"},{"key":"7271_CR22","doi-asserted-by":"crossref","first-page":"494","DOI":"10.1007\/978-3-540-27776-7_51","volume-title":"Proc. 4th Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS)","author":"I. Cimpian","year":"2004","unstructured":"I. Cimpian et al, \u201cCommunication optimization in Compaan Process Networks,\u201d in Proc. 4th Int. Workshop on Systems, Architectures, Modeling and Simulation (SAMOS), Samos, Greece, 2004, pp. 494\u2013506."},{"key":"7271_CR23","doi-asserted-by":"crossref","unstructured":"O. Bringmann and W. Rosenstiel, \u201cResource Sharing in Hierarchical Synthesis,\u201d in Proc. 1997 IEEE\/ACM International Conference on Computer-Aided Design (ICCAD), California, USA, 1997, pp. 318\u2013325.","DOI":"10.1109\/ICCAD.1997.643537"},{"key":"7271_CR24","doi-asserted-by":"crossref","unstructured":"Y. Yi, R. Woods and J. V. McCanny, \u201cHierarchical Synthesis of Complex DSP Functions on FPGAs,\u201d in Proc. 37th Asilomar Conference on Signals, Systems and Computers California, USA, 2003, pp. 1421\u20131426.","DOI":"10.1109\/ACSSC.2003.1292220"}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-006-7271-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-006-7271-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-006-7271-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,9]],"date-time":"2025-01-09T02:52:48Z","timestamp":1736391168000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-006-7271-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,6]]},"references-count":24,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[2006,6]]}},"alternative-id":["7271"],"URL":"https:\/\/doi.org\/10.1007\/s11265-006-7271-5","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[2006,6]]}}}