{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,9]],"date-time":"2025-01-09T05:33:51Z","timestamp":1736400831031,"version":"3.32.0"},"reference-count":18,"publisher":"Springer Science and Business Media LLC","issue":"2-3","license":[{"start":{"date-parts":[[2006,6,1]],"date-time":"2006-06-01T00:00:00Z","timestamp":1149120000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2006,6]]},"DOI":"10.1007\/s11265-006-7273-3","type":"journal-article","created":{"date-parts":[[2006,5,29]],"date-time":"2006-05-29T22:28:46Z","timestamp":1148941726000},"page":"235-246","source":"Crossref","is-referenced-by-count":5,"title":["Modeling Instruction Semantics in ADL Processor Descriptions for C Compiler Retargeting"],"prefix":"10.1007","volume":"43","author":[{"given":"Jianjiang","family":"Ceng","sequence":"first","affiliation":[]},{"given":"Weihua","family":"Sheng","sequence":"additional","affiliation":[]},{"given":"Manuel","family":"Hohenauer","sequence":"additional","affiliation":[]},{"given":"Rainer","family":"Leupers","sequence":"additional","affiliation":[]},{"given":"Gerd","family":"Ascheid","sequence":"additional","affiliation":[]},{"given":"Heinrich","family":"Meyr","sequence":"additional","affiliation":[]},{"given":"Gunnar","family":"Braun","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2006,6,1]]},"reference":[{"key":"7273_CR1","doi-asserted-by":"crossref","unstructured":"A. Hoffmann, R. Leupers, and H. Meyr. Architecture Exploration for Embedded Processors with LISA. Kluwer Academic Publishers, Boston, Jan. 2003. ISBN 1-4020-7338-0.","DOI":"10.1007\/978-1-4757-4538-2_1"},{"key":"7273_CR2","doi-asserted-by":"crossref","unstructured":"G. Braun, A. Nohl, W. Sheng, J. Ceng, M. Hohenauer, H. Scharwaechter, R. Leupers, and H. Meyr. A Novel Approach for Flexible and Consistent ADL-driven ASIP Design. Proc. of the Design Automation Conference (DAC), Mar. 2004.","DOI":"10.1145\/996566.996763"},{"key":"7273_CR3","unstructured":"S. Bashford, U. Bieker, B. Harking, R. Leupers, P. Marwedel, A. Neumann, and D. Voggenauer. The MIMOLA Language, Version 4.1. Reference Manual, Department of Computer Science 12, Embedded System Design and Didactics of Computer Science, 1994."},{"key":"7273_CR4","doi-asserted-by":"crossref","unstructured":"R. Leupers and P. Marwedel. A BDD-based frontend for retargetable compilers. In Proc. of the European Design and Test Conference (ED & TC), pages 239\u2013243, 1995.","DOI":"10.1109\/EDTC.1995.470389"},{"key":"7273_CR5","doi-asserted-by":"crossref","unstructured":"G. Hadjiyiannis, S. Hanono, and S. Devadas. ISDL: An Instruction Set Description Language for Retargetability. In Proc. of the Design Automation Conference (DAC), Jun. 1997.","DOI":"10.1109\/DAC.1997.597161"},{"key":"7273_CR6","doi-asserted-by":"crossref","unstructured":"Silvina Hanono and Srinivas Devadas. Instruction selection, resource allocation, and scheduling in the AVIV retargetable code generator. In Design Automation Conference, pages 510\u2013515, 1998.","DOI":"10.1145\/277044.277184"},{"key":"7273_CR7","doi-asserted-by":"crossref","unstructured":"A. Fauth, J. Van Praet, and M. Freericks. Describing Instruction Set Processors Using nML. In Proc. of the European Design and Test Conference (ED & TC), Mar. 1995.","DOI":"10.1109\/EDTC.1995.470354"},{"key":"7273_CR8","doi-asserted-by":"crossref","unstructured":"A. Halambi, P. Grun, V. Ganesh, A. Khare, N. Dutt, and A. Nicolau. EXPRESSION: A Language for Architecture Exploration through Compiler\/Simulator Retargetability. In Proc. of the Conference on Design, Automation & Test in Europe (DATE), Mar. 1999.","DOI":"10.1145\/307418.307549"},{"key":"7273_CR9","unstructured":"EXPRESSION User Manual (version 1.0) http:\/\/www.ics.uci.edu\/~express\/documentation.htm."},{"issue":"11","key":"7273_CR10","doi-asserted-by":"crossref","first-page":"1338","DOI":"10.1109\/43.959863","volume":"20","author":"A. Hoffmann","year":"2001","unstructured":"A. Hoffmann, T. Kogel, A. Nohl, G. Braun, O. Schliebusch, O. Wahlen, A. Wieferink, and H. Meyr. A Novel Methodology for the Design of Application Specific Instruction Set Processors (ASIP) Using a Machine Description Language. IEEE Transactions on Computer-Aided Design, 20(11):1338\u20131354, Nov. 2001.","journal-title":"IEEE Transactions on Computer-Aided Design"},{"key":"7273_CR11","unstructured":"CoWare Inc., www.coware.com . LISATek product family."},{"key":"7273_CR12","doi-asserted-by":"crossref","unstructured":"M. Hohenauer, H. Scharwaechter, K. Karuri, O. Wahlen, T. Kogel, R. Leupers, G. Ascheid, and H. Meyr. A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models. Proc. of the Conference on Design, Automation & Test in Europe (DATE), Mar. 2004.","DOI":"10.1109\/DATE.2004.1269071"},{"key":"7273_CR13","unstructured":"ACE \u2013 Associated Computer Experts bv. The COSY Compiler Development System http:\/\/www.ace.nl ."},{"key":"7273_CR14","doi-asserted-by":"crossref","unstructured":"J. Ceng, M. Hohenauer, R. Leupers, G. Ascheid, H. Meyr, and G. Braun. C compiler retargeting based on instruction semantics models. In DATE, pages 1150\u20131155, 2005.","DOI":"10.1109\/DATE.2005.88"},{"key":"7273_CR15","unstructured":"A. Aho, R. Sethi, and J. Ullman. Compilers, Principles, Techniques and Tools. Addison-Wesley, Jan. 1986. ISBN 0-2011-0088-6."},{"issue":"4","key":"7273_CR16","doi-asserted-by":"crossref","first-page":"491","DOI":"10.1145\/69558.75700","volume":"11","author":"A. Aho","year":"1989","unstructured":"A. Aho, M. Ganapathi, and S. Tjiang. Code generation using tree matching and dynamic programming. IEEE Transactions on Programming Languages and Systems, 11(4):491\u2013516, Oct. 1989.","journal-title":"IEEE Transactions on Programming Languages and Systems"},{"key":"7273_CR17","unstructured":"F. Homewood and P. Faraboschi. ST200: A VLIW Architecture for Media-Oriented Applications. In Microprocessor Forum, Oct. 2000."},{"key":"7273_CR18","unstructured":"X. Nie, L. Gazsi, F. Engel, and G. Fettweis. A new network processor architecture for high-speed communications. In Proc. of the IEEE Workshop on Signal Processing Systems (SIPS), pages 548\u2013557, Oct. 1999."}],"container-title":["Journal of VLSI signal processing systems for signal, image and video technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-006-7273-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-006-7273-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-006-7273-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,9]],"date-time":"2025-01-09T02:52:59Z","timestamp":1736391179000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-006-7273-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2006,6]]},"references-count":18,"journal-issue":{"issue":"2-3","published-print":{"date-parts":[[2006,6]]}},"alternative-id":["7273"],"URL":"https:\/\/doi.org\/10.1007\/s11265-006-7273-3","relation":{},"ISSN":["0922-5773"],"issn-type":[{"type":"print","value":"0922-5773"}],"subject":[],"published":{"date-parts":[[2006,6]]}}}