{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:27:47Z","timestamp":1747805267506,"version":"3.33.0"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2007,3,27]],"date-time":"2007-03-27T00:00:00Z","timestamp":1174953600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J VLSI Sign Process Syst Sign Im"],"published-print":{"date-parts":[[2007,10]]},"DOI":"10.1007\/s11265-007-0057-6","type":"journal-article","created":{"date-parts":[[2007,3,26]],"date-time":"2007-03-26T19:33:09Z","timestamp":1174937589000},"page":"87-99","source":"Crossref","is-referenced-by-count":25,"title":["Reliability-aware Co-synthesis for Embedded Systems"],"prefix":"10.1007","volume":"49","author":[{"given":"Y.","family":"Xie","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"L.","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M.","family":"Kandemir","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"N.","family":"Vijaykrishnan","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. J.","family":"Irwin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2007,3,27]]},"reference":[{"key":"57_CR1","unstructured":"BCC Research, http:\/\/www.bccresearch.com\/editors\/RG-229R.html ."},{"key":"57_CR2","doi-asserted-by":"crossref","unstructured":"Todd M. Austin, \u201cDIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design,\u201d in 32nd Annual International Symposium on Microarchitecture (MICRO), November 1999.","DOI":"10.1109\/MICRO.1999.809458"},{"key":"57_CR3","doi-asserted-by":"crossref","unstructured":"C. Bolchini, L. Pomante, F. Salice, and D. Sciuto, \u201cReliability Properties Assessment at System Level: a Co-design Framework,\u201d Online Testing Workshop, 2001.","DOI":"10.1109\/OLT.2001.937837"},{"key":"57_CR4","unstructured":"C. Bolchini, L. Pomante, F. Salice, and D. Sciuto, \u201cA System Level Approach in Design Dual-Duplex Fault Tolerant Embedded Systems,\u201d Online Testing Workshop, 2002."},{"key":"57_CR5","doi-asserted-by":"crossref","unstructured":"B. Dave and N. K. Jha, \u201cCOFTA: Hardware-Software co-synthesis of Heterogeneous Distributed Embedded Systems for Low Overhead Fault Tolerance,\u201d IEEE Trans. Comput., vol. 48, 1999.","DOI":"10.1109\/12.762534"},{"key":"57_CR6","doi-asserted-by":"crossref","unstructured":"R. P. Dick, D. L. Rhodes, and W. Wolf, \u201cTGFF: Task Graphs for Free,\u201d in Proc. Int. Workshop Hardware\/Software Codesign, 1998, pp. 97\u2013101.","DOI":"10.1145\/278241.278309"},{"key":"57_CR7","doi-asserted-by":"crossref","unstructured":"A. Orailoglu and R. Karri, \u201cA Design Methodology for the High-level Synthesis of Fault-tolerant Asics,\u201d VLSI Signal Proc. V, 1992, pp. 417\u2013426.","DOI":"10.1109\/VLSISP.1992.641073"},{"key":"57_CR8","doi-asserted-by":"crossref","unstructured":"D. Mavis and P. Eaton, \u201cSoft Error Rate Mitigation Techniques for Modern Microcircuits,\u201d in Proc. Reliable Physics Symposium, 2002, pp. 216\u2013225.","DOI":"10.1109\/RELPHY.2002.996639"},{"key":"57_CR9","doi-asserted-by":"crossref","unstructured":"K. Mohanram and N. Touba, \u201cCost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits,\u201d ITC, 2003.","DOI":"10.1109\/TEST.2003.1271075"},{"key":"57_CR10","doi-asserted-by":"crossref","unstructured":"Shubhendu S. Mukherjee, Mike Kontz, and Steven K. Reinhardt, \u201cDetailed Design and Implementation of Redundant Multithreading Alternatives,\u201d in Proceedings of the 29th Annual International Symposium on Computer Architecture (ISCA), 2002.","DOI":"10.1109\/ISCA.2002.1003566"},{"key":"57_CR11","unstructured":"Y. Xie and W. Wolf, \u201cASICosyn: Co-synthesis of Coditional Task Graphs with Custom ASICs,\u201d in Proceedings of the International Conference on ASICs, 2001. pp. 130\u2013135."},{"key":"57_CR12","unstructured":"Actel Coroporation, \u201cEffects of Neutrons on Programmable Logic,\u201d White Paper, 2002."},{"key":"57_CR13","doi-asserted-by":"crossref","unstructured":"Wayne Wolf and Jorgen Staunstrup, Hardware\/Software Co-design Principles and Practice, Kluwer, 1997.","DOI":"10.1007\/978-1-4757-2649-7"},{"issue":"1","key":"57_CR14","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1147\/rd.401.0003","volume":"40","author":"J. F. Ziegler","year":"1996","unstructured":"J. F. Ziegler et al. \u201cIBM Experiments in Soft Fails in Computer Electronics (1978\u20131994),\u201d IBM J. Res. Develop., vol. 40, no. 1, 1996, pp. 3\u201318.","journal-title":"IBM J. Res. Develop."},{"key":"57_CR15","unstructured":"B. Johnson, Design and Analysis of Fault-tolerant Digital Systems, Addison-Wesley, 1989."},{"key":"57_CR16","doi-asserted-by":"crossref","unstructured":"H. Hollander, B. Carlson, and T. Bennett, \u201cSynthesis of SEU-Tolerant ASICs Using Concurrent Error Corretion,\u201d in Proceedings of IEEE Great Lake VLSI Symposium, 1995, pp. 90\u201393.","DOI":"10.1109\/GLSV.1995.516031"},{"issue":"3","key":"57_CR17","doi-asserted-by":"crossref","first-page":"404","DOI":"10.1109\/24.536993","volume":"45","author":"R. Karri","year":"1996","unstructured":"R. Karri and A. Orailoglu, \u201cTime-constrained Scheduling during High-level Synthesis of Fault-secure,\u201d VLSI Digital Signal Processors, IEEE Transaction on Reliability, vol. 45, no. 3, 1996, pp. 404\u2013413.","journal-title":"VLSI Digital Signal Processors, IEEE Transaction on Reliability"},{"key":"57_CR18","doi-asserted-by":"crossref","unstructured":"Yanbing L`i, and J\u00f6rg Henkel, \u201cA Framework for Estimation and Minimizing Energy Dissipation of Embedded HW\/SW Systems,\u201d in Proceedings of DAC, 1998, pp. 188\u2013193.","DOI":"10.1145\/277044.277097"},{"key":"57_CR19","doi-asserted-by":"crossref","unstructured":"C. Constantinescu, \u201cTrends and Challenges in VLSI Circuits Reliability,\u201d IEEE Micro, July\u2013August, 2003.","DOI":"10.1109\/MM.2003.1225959"},{"key":"57_CR20","doi-asserted-by":"crossref","unstructured":"S. Tosun, O. Ozturk, N. Mansouri, E. Arvas, M. Kandemir, and Y. Xie, \u201cAn ILP Formulation for Reliability-oriented High-level Synthesis,\u201d in Proceedings of the Sixth International Symposium on Quality Electronic Design (ISQED 2005). San Jose, CA, 22, 2005.","DOI":"10.1109\/ISQED.2005.15"},{"key":"57_CR21","unstructured":"G.Micheli, R. Ernst, and W. Wolf, Readings in Hardware\/Software Co-design, Morgan Kaufmann, 2002."},{"key":"57_CR22","doi-asserted-by":"crossref","unstructured":"W. Wolf, \u201cA Decade of Hardware\/Software Co-design,\u201d IEEE Computer, 2003, pp. 38\u201343.","DOI":"10.1109\/MC.2003.1193227"},{"key":"57_CR23","unstructured":"R. P.Dick, \u201cMultiobjective Synthesis of Low-power Real-time Distributed Embedded Systems,\u201d Ph.D. thesis, Princeton University, 2002."},{"key":"57_CR24","doi-asserted-by":"crossref","first-page":"17","DOI":"10.1016\/0167-6377(89)90027-8","volume":"8","author":"D. Coppersmith","year":"1989","unstructured":"D. Coppersmith and P. Raghavan, \u201cMultidimensional Online Bin Packing: Algorithms and Worst Case Analysis,\u201d Oper. Res. Lett., vol. 8, 1989, pp. 17\u201320.","journal-title":"Oper. Res. Lett."}],"container-title":["The Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0057-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-007-0057-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0057-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,15]],"date-time":"2025-01-15T06:52:42Z","timestamp":1736923962000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-007-0057-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,3,27]]},"references-count":24,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2007,10]]}},"alternative-id":["57"],"URL":"https:\/\/doi.org\/10.1007\/s11265-007-0057-6","relation":{},"ISSN":["0922-5773","1573-109X"],"issn-type":[{"type":"print","value":"0922-5773"},{"type":"electronic","value":"1573-109X"}],"subject":[],"published":{"date-parts":[[2007,3,27]]}}}