{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,18]],"date-time":"2025-01-18T05:27:21Z","timestamp":1737178041259,"version":"3.33.0"},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2007,6,28]],"date-time":"2007-06-28T00:00:00Z","timestamp":1182988800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s11265-007-0059-4","type":"journal-article","created":{"date-parts":[[2007,6,27]],"date-time":"2007-06-27T21:13:20Z","timestamp":1182978800000},"page":"269-288","source":"Crossref","is-referenced-by-count":4,"title":["Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores"],"prefix":"10.1007","volume":"51","author":[{"given":"Yung-Chia","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia Han","family":"Lu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Ju","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Lin","family":"Tang","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yi-Ping","family":"You","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ya-Chaio","family":"Moo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jenq-Kuen","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2007,6,28]]},"reference":[{"key":"59_CR1","unstructured":"The SUIF 2 compiler system, http:\/\/suif.stanford.edu\/suif\/suif2 ."},{"key":"59_CR2","doi-asserted-by":"crossref","unstructured":"P.P. Chang et al., \u201cIMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors,\u201d in Proceedings of the 18th Annual International Symposium on Computer Architecture, Toronto, Canada, vol. 28, no. 5 1991, pp. 266\u2013275.","DOI":"10.1145\/115952.115979"},{"key":"59_CR3","unstructured":"ReaCT-ILP Laboratory, \u201cTrimaran: An Infrastructure for Research in Instruction-Level Parallelism,\u201d http:\/\/www.trimaran.org ."},{"key":"59_CR4","unstructured":"A. Andrew et al., \u201cThe Zephyr Compiler Infrastructure,\u201d http:\/\/www.cs.virginia.edu\/zephyr\/ ."},{"key":"59_CR5","unstructured":"The GNU Compiler Collection, http:\/\/gcc.gnu.org ."},{"key":"59_CR6","unstructured":"R. Ju, S. Chan and C. Wu, \u201cOpen Research Compiler for the Itanium Family,\u201d Tutorial at the 34th Annual International Symposium on Microarchitecture, Dec. 2001."},{"key":"59_CR7","unstructured":"G.R. Gao, J.N. Amaral, J. Dehnert and R. Towle, \u201cThe SGI Pro64 compiler infrastructure: A tutorial,\u201d in Tutorial at the International Conference on Parallel Architecture and Compilation Techniques, Oct. 2000."},{"key":"59_CR8","unstructured":"T.-J. Lin, C.-C. Lee, C.-W. Liu and C.-W. Jen, \u201cA Novel Register Organization for VLIW Digital Signal Processors,\u201d in Proc. of 2005 IEEE Int. Symp. on VLSI Design, Automation, and Test, 2005, pp. 335\u2013338."},{"key":"59_CR9","unstructured":"T.-J. Lin, P.-C. Hsiao, C.-W. Liu and C.-W. Jen, \u201cArea-Efficient Register Organization for Fully-Synthesizable VLIW DSP Cores\u201d, International Journal of Electrical Engineering, vol. 13, May 2006."},{"key":"59_CR10","unstructured":"D. Chang and M. Baron, \u201cTaiwan\u2019s Roadmap to Leadership in Design,\u201d Microprocessor Report, In-Stat\/MDR, Dec. 2004. http:\/\/www.mdronline.com\/mpr\/archive\/mpr\\_2004.html ."},{"key":"59_CR11","doi-asserted-by":"crossref","unstructured":"D.C.-W. Chang, C.-W. Jen, I-T. Liao, J.-K. Lee, W.-F. Chen and S.-Y. Tseng, \u201c PAC DSP Core and Application Processors,\u201d in Proc. of the IEEE Int. Conf. on Multimedia & Expo, Toronto, July 9\u201312, 2006.","DOI":"10.1109\/ICME.2006.262455"},{"key":"59_CR12","unstructured":"T.-J. Lin, C.-C. Chang, C.-C. Lee and C.-W. Jen, \u201cAn Efficient VLIW DSP Architecture for Baseband Processing,\u201d in Proceedings of the 21th International Conference on Computer Design, 2003."},{"key":"59_CR13","doi-asserted-by":"crossref","unstructured":"T.-J. Lin, C.-M. Chao, C.-H. Liu, P.-C. Hsiao, S.-K. Chen, L.-C. Lin, C.-W. Liu, C.-W. Jen, \u201cComputer Architecture: A Unified Processor Architecture for RISC & VLIW DSP,\u201d in Proceedings of the 15th ACM Great Lakes symposium on VLSI, April 2005.","DOI":"10.1145\/1057661.1057675"},{"key":"59_CR14","unstructured":"TMS320DM6443 Digital Media System-on-Chip Datasheet, Texas Instruments, 2006."},{"key":"59_CR15","doi-asserted-by":"crossref","unstructured":"S. Rixner, W.J. Dally, B. Khailany, P. Mattson, U.J. Kapasi and J.D. Owens, \u201cRegister organization for media processing,\u201d in International Symposium on High Performance Computer Architecture (HPCA), pp. 375\u2013386, 2000.","DOI":"10.1109\/HPCA.2000.824366"},{"key":"59_CR16","unstructured":"A. Capitanio, N. Dutt and A. Nicolau, \u201cPartitioned register files for VLIW\u2019s: A preliminary analysis of tradeoffs,\u201d in Procs. of the 25th Int. Symp. on Microarchitecture: Portland, OR, December 1\u20134, 1992, pp. 292\u2013300."},{"key":"59_CR17","doi-asserted-by":"crossref","unstructured":"A. Terechko, E.L. Thenaff, M. Garg, Eijndhoven and H. Corporaal, \u201cInter-cluster communication models for clustered VLIW processors,\u201d in Procs. HPCA, 2003, pp. 354\u2013364.","DOI":"10.1145\/951710.951717"},{"key":"59_CR18","unstructured":"WHIRL Intermediate Language Specification, \u201cSGI,\u201d 2000."},{"key":"59_CR19","unstructured":"Y.-P. You, C.-R. Lee and J.K. Lee, \u201cCompiler Analysis and Supports for Leakage Power Reduction on Microprocessors,\u201d in LCPC\u201902, USA, July 2002."},{"issue":"2","key":"59_CR20","doi-asserted-by":"crossref","first-page":"252","DOI":"10.1145\/762488.762494","volume":"8","author":"C.-R. Lee","year":"2003","unstructured":"C.-R. Lee, J.-K. Lee, T.-T. Hwang and S.-C. Tsai, \u201cCompiler Optimizations on VLIW Instruction Scheduling for Low Power,\u201d ACM Transact. Des. Automat. Electron. Syst., vol. 8, no. 2, 2003, pp. 252\u2013268.","journal-title":"ACM Transact. Des. Automat. Electron. Syst."},{"key":"59_CR21","doi-asserted-by":"crossref","unstructured":"Y.-P. You, C.-W. Huang and J.-K. Lee, A Sink-N-Hoist Framework for Leakage Power Reduction,\u201d in Proceedings of ACM EMSOFT 2005, September 2005.","DOI":"10.1145\/1086228.1086252"},{"key":"59_CR22","doi-asserted-by":"crossref","unstructured":"P.-S. Chen, M.-Y. Hung, Y.-S. Hwang, R. D.-C. Ju and J.K. Lee, \u201cCompiler Support for Speculative Multithreading Architecture with Probabilistic Points-To Analysis,\u201d in Proceedings of ACM Principles and Practices of Parallel Programming (ACM PPoPP), San Diego, 2003.","DOI":"10.1145\/781498.781502"},{"issue":"10","key":"59_CR23","doi-asserted-by":"crossref","first-page":"893","DOI":"10.1109\/TPDS.2004.56","volume":"15","author":"P.-S. Chen","year":"2004","unstructured":"P.-S. Chen, Y.-S. Hwang, D.-C. Ju and J.K. Lee, \u201cInterprocedural Probabilistic Pointer Analysis,\u201d IEEE Trans. Parallel Distrib. Syst., vol. 15, no. 10, Oct. 2004, pp. 893\u2013907.","journal-title":"IEEE Trans. Parallel Distrib. Syst."},{"key":"59_CR24","unstructured":"Y.-C. Lin, Y.-S. Hwang and J.K. Lee, \u201cCompiler Optimizations with DSP-Specific Semantic Descriptions,\u201d in LCPC\u201902, USA, July 2002."},{"key":"59_CR25","unstructured":"John R. Hauser. SoftFloat. http:\/\/www.jhauser.us\/arithmetic\/SoftFloat.html ."},{"key":"59_CR26","unstructured":"C.-W. Chen, C.-L. Tang, Y.-C. Lin and J.-K. Lee, \u201cORC2DSP: Compiler Infrastructure Supports for VLIW DSP Processors,\u201d in Proceedings of 2005 IEEE International Symposium on VLSI Design, Automation, and Test, 2005, pp. 224\u2013227."},{"issue":"4598","key":"59_CR27","doi-asserted-by":"crossref","first-page":"671","DOI":"10.1126\/science.220.4598.671","volume":"220","author":"S. Kirkpatrick","year":"1983","unstructured":"S. Kirkpatrick, C.D. Gelatt and M.P. Vecchi, \u201cOptimization by Simulated Annealing,\u201d Science, vol. 220, no. 4598, 1983, pp. 671\u2013680.","journal-title":"Science"},{"key":"59_CR28","doi-asserted-by":"crossref","unstructured":"P. Salamon, P. Sibani and R. Frost, \u201cFacts, Conjectures, and Improvements for Simulated Annealing. ser. Monographs on Mathematical Modeling and Computation,\u201d Society for Industrial and Applied Mathematics, no. 7, 2002.","DOI":"10.1137\/1.9780898718300"},{"key":"59_CR29","doi-asserted-by":"crossref","unstructured":"R. Leupers, \u201cInstruction scheduling for clustered VLIW DSPs,\u201d in Proc. Int\u2019l Conference on Parallel Architecture and Compilation Techniques, Oct. 2000, pp. 291\u2013300.","DOI":"10.1109\/PACT.2000.888353"},{"key":"59_CR30","unstructured":"Y.-C. Lin, Y.-P. You and J.-K. Lee, \u201cRegister Allocation for VLIW DSP Processors with Irregular Register Files,\u201d in CPC 2006, Spain, Jan. 2006."},{"key":"59_CR31","unstructured":"A.V. Aho, R. Sethi and J.D. Ullman, \u201cCompilers: Principles, Techniques and Tools,\u201d Addison-Wesley, November 1985."},{"key":"59_CR32","unstructured":"M.E. Wolf, D.E. Maydan and D.-K. Chen, \u201cCombining loop transformations considering caches and scheduling,\u201d International Journal of Parallel Programming, vol. 26, no. 4, 1998."},{"key":"59_CR33","unstructured":"V. Zivojnovic, J. Martinez, C. Schl\u00e4ger and H. Meyr, \u201cDSPstone: A DSP-Oriented Benchmarking Methodology,\u201d Proc. of ICSPAT, Dallas, 1994."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0059-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-007-0059-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0059-4","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,17]],"date-time":"2025-01-17T22:51:17Z","timestamp":1737154277000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-007-0059-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,6,28]]},"references-count":33,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["59"],"URL":"https:\/\/doi.org\/10.1007\/s11265-007-0059-4","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2007,6,28]]}}}