{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,1,21]],"date-time":"2025-01-21T05:13:19Z","timestamp":1737436399576,"version":"3.33.0"},"reference-count":32,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2007,8,20]],"date-time":"2007-08-20T00:00:00Z","timestamp":1187568000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image"],"published-print":{"date-parts":[[2008,6]]},"DOI":"10.1007\/s11265-007-0061-x","type":"journal-article","created":{"date-parts":[[2007,8,19]],"date-time":"2007-08-19T19:00:48Z","timestamp":1187550048000},"page":"209-223","source":"Crossref","is-referenced-by-count":15,"title":["Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications"],"prefix":"10.1007","volume":"51","author":[{"given":"Tay-Jyi","family":"Lin","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shin-Kai","family":"Chen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yu-Ting","family":"Kuo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chih-Wei","family":"Liu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pi-Chen","family":"Hsiao","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2007,8,20]]},"reference":[{"key":"61_CR1","doi-asserted-by":"crossref","unstructured":"P. Lapsley, J. Bier, and E. A. Lee, \u201cDSP Processor Fundamentals - Architectures and Features,\u201d IEEE Press, 1996.","DOI":"10.1109\/9780470544433"},{"key":"61_CR2","unstructured":"Y. H. Hu, \u201cProgrammable Digital Signal Processors\u2014Architecture, Programming, and Applications,\u201d Marcel Dekker, 2002."},{"key":"61_CR3","unstructured":"J. A. Fisher, P. Faraboschi, and C. Young, \u201cEmbedded Computing\u2014A VLIW Approach to Architecture, Compiler, and Tools,\u201d Morgan Kaufmann, 2005."},{"key":"61_CR4","doi-asserted-by":"crossref","unstructured":"S. Rixner, W. J. Dally, B. Khailany, P. Mattson, U. J. Kapasi, and J. D. Owens, \u201cRegister Organization for Media Processing,\u201d in Proc. HPCA, 2000, pp. 375\u2013386.","DOI":"10.1109\/HPCA.2000.824366"},{"key":"61_CR5","doi-asserted-by":"crossref","unstructured":"A. Terechko, E. L. Thenaff, M. Garg, J. Eijndhoven and H. Corporaal, \u201cInter-Cluster Communication Models for Clustered VLIW Processors,\u201d in Proc. HPCA, 2003, pp. 354\u2013364.","DOI":"10.1109\/HPCA.2003.1183552"},{"key":"61_CR6","first-page":"117","volume":"13","author":"T. J. Lin","year":"2006","unstructured":"T. J. Lin, P. C. Hsiao, C. W. Liu, and C. W. Jen, \u201cArea-Efficient Register Organization for Fully-Synthesizable VLIW DSP Cores,\u201d Int. J. Electr. Eng., vol. 13, pp. 117\u2013127, May 2006.","journal-title":"Int. J. Electr. Eng."},{"key":"61_CR7","doi-asserted-by":"crossref","unstructured":"P. Faraboschi, G. Brown, J. A. Fisher, G. Desoll and F. M. O. Homewood, \u201cLx: A Technology Platform for Customizable VLIW Embedded Processing,\u201d in Proc. ISCA, 2000, pp. 203\u2013213.","DOI":"10.1145\/339647.339682"},{"key":"61_CR8","doi-asserted-by":"crossref","unstructured":"G. G. Pechanek and S. Vassiliadis, \u201cThe ManArray Embedded Processor Architecture,\u201d in Proc. Euromicro Conf., 2000, pp. 348\u2013355.","DOI":"10.1109\/EURMIC.2000.874652"},{"key":"61_CR9","unstructured":"TMS320C64x DSP Generation. http:\/\/www.ti.com ."},{"key":"61_CR10","unstructured":"K. Arora, H. Sharangpani, and R. Gupta, \u201cCopied Register Files for Data Processors Having Many Execution Units,\u201d US Patent 6,629,232, Sep. 30, 2003."},{"key":"61_CR11","doi-asserted-by":"crossref","first-page":"1609","DOI":"10.1109\/4.962280","volume":"36","author":"A. Kowalczyk","year":"2001","unstructured":"A. Kowalczyk et al., \u201cThe First MAJC Microprocessor: A Dual CPU System-On-a-Chip,\u201d IEEE J. Solid-State Circuits, vol. 36, pp. 1609\u20131616, Nov. 2001.","journal-title":"IEEE J. Solid-State Circuits"},{"key":"61_CR12","unstructured":"T. J. Lin et al., \u201cPerformance Evaluation of Ring-Structure Register File in Multimedia Applications,\u201d in Proc. ICME, July 2003."},{"key":"61_CR13","unstructured":"A. V. Oppenheim, R. W. Schafer, and J. R. Buck, \u201cDiscrete-Time Signal Processing, 2nd ed.,\u201d Prentice Hall, 1999."},{"key":"61_CR14","unstructured":"Independent JPEG Group. http:\/\/www.ijg.org ."},{"key":"61_CR15","doi-asserted-by":"crossref","unstructured":"H. Pan and K. Asanovic, \u201cHeads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode,\u201d in Proc. CASES, 2001.","DOI":"10.1145\/502217.502244"},{"key":"61_CR16","doi-asserted-by":"crossref","unstructured":"T. Kumura, M. Ikekawa, M. Yoshida, and I. Kuroda, \u201cVLIW DSP for Mobile Applications,\u201d IEEE Signal Process. Mag., pp. 10\u201321, July 2002.","DOI":"10.1109\/MSP.2002.1012346"},{"key":"61_CR17","unstructured":"G. Fettweis, M. Bolle, J. Kneip, and M. Weiss, \u201cOnDSP: A New Architecture for Wireless LAN Applications,\u201d Presented at Embedded Processor Forum, San Jose, 2002."},{"key":"61_CR18","doi-asserted-by":"crossref","unstructured":"T. J. Lin et al., \u201cA Unified Processor Architecture for RISC & VLIW DSP,\u201d in Proc. GLSVLSI, Apr. 2005.","DOI":"10.1145\/1057661.1057675"},{"key":"61_CR19","unstructured":"TMS320C55x DSP Generation. http:\/\/www.ti.com ."},{"key":"61_CR20","doi-asserted-by":"crossref","unstructured":"R. K. Kolagotla et al., \u201cHigh-Performance Dual-MAC DSP Architecture,\u201d IEEE Signal Process. Mag., pp. 42\u201353, July 2002.","DOI":"10.1109\/MSP.2002.1012349"},{"key":"61_CR21","unstructured":"J. P. Shen and M. H. Lipasti, \u201cModern Processor Design\u2014Fundamental of Superscalar Processors,\u201d McGraw-Hill, 2005."},{"key":"61_CR22","unstructured":"M. Keating and P. Bricaud, \u201cReuse Methodology Manual\u2014For System-on-a-Chip Designs, 3rd ed.,\u201d Kluwer, 2002."},{"key":"61_CR23","unstructured":"D. Chinnery and K. Keutzer, \u201cClosing the Gap Between ASIC & Custom\u2014Tools and Techniques for High-Performance ASIC Design,\u201d Kluwer, 2002."},{"key":"61_CR24","unstructured":"J. Bhasker, \u201cA SystemC Primer,\u201d Star Galaxy Publishing, 2002."},{"key":"61_CR25","doi-asserted-by":"crossref","unstructured":"J. Bergeron, \u201cWriting Testbenches\u2014Functional Verification of HDL Models, 2nd ed.,\u201d Kluwer, 2003.","DOI":"10.1007\/978-1-4615-0302-6"},{"key":"61_CR26","unstructured":"Versatile Platform Baseboard for ARM926EJ-S. http:\/\/www.arm.com\/ ."},{"key":"61_CR27","doi-asserted-by":"crossref","unstructured":"I. E. G. Richardson, \u201cH.264 and MPEG-4 Video Compression,\u201d Wiley, 2003.","DOI":"10.1002\/0470869615"},{"key":"61_CR28","unstructured":"J. L Hennessy and D. A. Patterson, Computer Architecture\u2014A Quantitative Approach, 3rd ed.,\u201d Morgan Kaufmann, 2002."},{"key":"61_CR29","unstructured":"W. B. Pennebaker and J. L. Mitchell, JPEG\u2014Still Image Data Compression Standard, Van Nostrand Reinhold, 1993."},{"key":"61_CR30","unstructured":"Y. C. Lin, Y. P. You, and J. K. Lee, \u201cRegister Allocation for VLIW DSP Processors with Irregular Register Files,\u201d in Proc. CPC, 2006."},{"key":"61_CR31","unstructured":"Intel 64 and IA-32 Architectures Software Developer\u2019s Manual, Intel, Nov. 2006."},{"key":"61_CR32","unstructured":"The Thumb Architecture Extension. http:\/\/www.arm.com ."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0061-x.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-007-0061-x\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0061-x","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,1,20]],"date-time":"2025-01-20T13:23:06Z","timestamp":1737379386000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-007-0061-x"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2007,8,20]]},"references-count":32,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2008,6]]}},"alternative-id":["61"],"URL":"https:\/\/doi.org\/10.1007\/s11265-007-0061-x","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2007,8,20]]}}}