{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,27]],"date-time":"2025-10-27T15:56:08Z","timestamp":1761580568460},"reference-count":21,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2008,1,17]],"date-time":"2008-01-17T00:00:00Z","timestamp":1200528000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image"],"published-print":{"date-parts":[[2008,2]]},"DOI":"10.1007\/s11265-007-0158-2","type":"journal-article","created":{"date-parts":[[2008,1,16]],"date-time":"2008-01-16T16:36:14Z","timestamp":1200501374000},"page":"251-261","source":"Crossref","is-referenced-by-count":27,"title":["Area, Delay, and Power Characteristics of Standard-Cell Implementations of the AES S-Box"],"prefix":"10.1007","volume":"50","author":[{"given":"Stefan","family":"Tillich","sequence":"first","affiliation":[]},{"given":"Martin","family":"Feldhofer","sequence":"additional","affiliation":[]},{"given":"Thomas","family":"Popp","sequence":"additional","affiliation":[]},{"given":"Johann","family":"Gro\u00dfsch\u00e4dl","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2008,1,17]]},"reference":[{"key":"158_CR1","doi-asserted-by":"crossref","unstructured":"Bertoni, G., Macchetti, M., Negri, L., & Fragneto, P. (2004). Power-efficient ASIC synthesis of cryptographic Sboxes. In Proceedings of the 14th ACM Great Lakes Symposium on VLSI (GLSVLSI 2004) (pp. 277\u2013281). ACM Press.","DOI":"10.1145\/988952.989019"},{"key":"158_CR2","doi-asserted-by":"crossref","unstructured":"Canright, D. (2005). A very compact S-Box for AES. In Cryptographic Hardware and Embedded Systems\u2014CHES 2005, vol. 3659 of Lecture Notes in Computer Science (pp. 441\u2013455). Springer.","DOI":"10.1007\/11545262_32"},{"key":"158_CR3","doi-asserted-by":"crossref","unstructured":"Chodowiec, P., & Gaj, K. (2003). Very compact FPGA implementation of the AES algorithm. In Cryptographic Hardware and Embedded Systems\u2014CHES 2003, vol. 2779 of Lecture Notes in Computer Science (pp. 319\u2013333). Springer.","DOI":"10.1007\/978-3-540-45238-6_26"},{"key":"158_CR4","doi-asserted-by":"crossref","unstructured":"Daemen, J., & Rijmen, V. (2002). The Design of Rijndael: AES\u2014The Advanced Encryption Standard. Springer.","DOI":"10.1007\/978-3-662-04722-4"},{"key":"158_CR5","unstructured":"Feldhofer, M., Lemke, K., Oswald, E., Standaert, F.-X., Wollinger, T., & Wolkerstorfer, J. (2005). State of the Art in Hardware Architectures. ECRYPT deliverable D.VAM.2, available for download at http:\/\/www.ecrypt.eu.org\/documents\/D.VAM.2-1.0.pdf , Sept."},{"issue":"1","key":"158_CR6","doi-asserted-by":"crossref","first-page":"13","DOI":"10.1049\/ip-ifs:20055006","volume":"152","author":"M. Feldhofer","year":"2005","unstructured":"Feldhofer, M., Wolkerstorfer, J., & Rijmen, V. (2005). AES implementation on a grain of sand. IEE Proceedings Information Security, 152(1), 13\u201320, Oct.","journal-title":"IEE Proceedings Information Security"},{"key":"158_CR7","doi-asserted-by":"crossref","unstructured":"Hodjat, A., Hwang, D. D., Lai, B.-C\u00a0., Tiri, K., & Verbauwhede, I. M. (2005). A 3.84\u00a0Gbits\/s AES crypto coprocessor with modes of operation in a 0.18-\u03bcm CMOS technology. In Proceedings of the 15th ACM Great Lakes Symposium on VLSI (GLSVLSI 2005) (pp. 351\u2013356). ACM Press.","DOI":"10.1145\/1057661.1057677"},{"key":"158_CR8","doi-asserted-by":"crossref","unstructured":"Li, H. (2004). A parallel S-box architecture for AES byte substitution. In Proceedings of the 2nd International Conference on Communications, Circuits and Systems (ICCCAS 2004), vol. 1 (pp. 1\u20133). IEEE.","DOI":"10.1109\/ICCCAS.2004.1345925"},{"key":"158_CR9","unstructured":"Lidl, R., & Niederreiter, H. (1996). Finite Fields, vol. 20 of Encyclopedia of Mathematics and Its Applications. Cambridge University Press."},{"issue":"0","key":"158_CR10","first-page":"84","volume":"0","author":"M. Macchetti","year":"2003","unstructured":"Macchetti, M., & Bertoni, G. (2003). Hardware implementation of the Rijndael SBOX: A case study. ST Journal of System Research, 0(0), 84\u201391, July.","journal-title":"ST Journal of System Research"},{"key":"158_CR11","doi-asserted-by":"crossref","unstructured":"McLoone, M., & McCanny, J. V. (2001). High performance single-chip FPGA Rijndael algorithm implementations. In Cryptographic Hardware and Embedded Systems\u2014CHES 2001, vol. 2162 of Lecture Notes in Computer Science (pp. 65\u201376). Springer.","DOI":"10.1007\/3-540-44709-1_7"},{"key":"158_CR12","doi-asserted-by":"crossref","unstructured":"Mentens, N., Batina, L., Preneel, B., & Verbauwhede, I. M. (2005). Systematic evaluation of compact hardware implementations for the Rijndael S-box. In Topics in Cryptology\u2014CT-RSA 2005, vol. 3376 of Lecture Notes in Computer Science (pp. 323\u2013333). Springer.","DOI":"10.1007\/978-3-540-30574-3_22"},{"key":"158_CR13","unstructured":"Morioka, S., & Satoh, A. (2002). An optimized S-Box circuit architecture for low power AES design. In Cryptographic Hardware and Embedded Systems\u2013CHES 2002, vol. 2523 of Lecture Notes in Computer Science (pp. 172\u2013186). Springer."},{"key":"158_CR14","unstructured":"National Institute of Standards and Technology (NIST) (1999). Data Encryption Standard (DES). Federal Information Processing Standards (FIPS) Publication 46-3, Oct."},{"key":"158_CR15","unstructured":"National Institute of Standards and Technology (NIST) (2001). Advanced Encryption Standard (AES). Federal Information Processing Standards (FIPS) Publication 197, Nov."},{"key":"158_CR16","doi-asserted-by":"crossref","unstructured":"Pramstaller, N., & Wolkerstorfer, J. (2004). A universal and efficient AES co-processor for field programmable logic arrays. In Field Programmable Logic and Application\u2014FPL 2004, vol. 3203 of Lecture Notes in Computer Science (pp. 565\u2013574). Springer.","DOI":"10.1007\/978-3-540-30117-2_58"},{"key":"158_CR17","doi-asserted-by":"crossref","unstructured":"Satoh, A., Morioka, S., Takano, K., & Munetoh, S. (2001). A compact Rijndael hardware architecture with S-Box optimization. In Advances in Cryptology\u2014ASIACRYPT 2001, vol. 2248 of Lecture Notes in Computer Science (pp. 239\u2013254). Springer.","DOI":"10.1007\/3-540-45682-1_15"},{"key":"158_CR18","unstructured":"Tillich, S., Feldhofer, M., & Gro\u00dfsch\u00e4dl, J. (2006). Area, delay, and power characteristics of standard-cell implementations of the AES S-box. In Embedded Computer Systems: Architectures, Modeling, and Simulation\u2014SAMOS 2006, vol. 4017 of Lecture Notes in Computer Science (pp. 457\u2013466). Springer."},{"key":"158_CR19","doi-asserted-by":"crossref","unstructured":"Tillich, S., & Gro\u00dfsch\u00e4dl, J. (2006). Instruction set extensions for efficient AES implementation on 32-bit processors. In Cryptographic Hardware and Embedded Systems\u2014CHES 2006, vol. 4249 of Lecture Notes in Computer Science (pp. 270\u2013284). Springer.","DOI":"10.1007\/11894063_22"},{"key":"158_CR20","doi-asserted-by":"crossref","unstructured":"Wolkerstorfer, J., Oswald, E., & Lamberger, M. (2002). An ASIC implementation of the AES SBoxes. In Topics in Cryptology\u2014CT-RSA 2002, vol. 2271 of Lecture Notes in Computer Science (pp. 67\u201378). Springer.","DOI":"10.1007\/3-540-45760-7_6"},{"issue":"9","key":"158_CR21","doi-asserted-by":"crossref","first-page":"957","DOI":"10.1109\/TVLSI.2004.832943","volume":"12","author":"X. Zhang","year":"2004","unstructured":"Zhang, X., & Parhi, K. K. (2004). High-speed VLSI architectures for the AES algorithm. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(9), 957\u2013967, Sept.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0158-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-007-0158-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-007-0158-2","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T12:19:27Z","timestamp":1559391567000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-007-0158-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,1,17]]},"references-count":21,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2008,2]]}},"alternative-id":["158"],"URL":"https:\/\/doi.org\/10.1007\/s11265-007-0158-2","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,1,17]]}}}