{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,3]],"date-time":"2022-04-03T06:28:38Z","timestamp":1648967318588},"reference-count":9,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2008,7,12]],"date-time":"2008-07-12T00:00:00Z","timestamp":1215820800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1007\/s11265-008-0252-0","type":"journal-article","created":{"date-parts":[[2008,7,11]],"date-time":"2008-07-11T10:42:17Z","timestamp":1215772937000},"page":"17-23","source":"Crossref","is-referenced-by-count":1,"title":["Design and FPGA-Implementation of a High Performance Timing Recovery Loop for Broadband Communications"],"prefix":"10.1007","volume":"56","author":[{"given":"V.","family":"Torres","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"A.","family":"P\u00e9rez-Pascual","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"T.","family":"Sansaloni","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Valls","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,7,12]]},"reference":[{"key":"252_CR1","unstructured":"European Telecommunications Standards Institute. (1997). Digital video broadcasting (DVB): Framing structure, channel coding and modulation for 11\/12\u00a0GHz satellite services. European standard (Telecommunications series), EN 300 421 V1.1.2."},{"key":"252_CR2","volume-title":"VLSI digital signal processing: design and implementation","author":"K. K. Parhi","year":"1999","unstructured":"Parhi, K. K. (1999). VLSI digital signal processing: design and implementation. New York: Wiley."},{"key":"252_CR3","doi-asserted-by":"crossref","DOI":"10.1002\/0471732699","volume-title":"Phaselock techniques","author":"F. M. Gardner","year":"2005","unstructured":"Gardner, F. M. (2005). Phaselock techniques. New York: Wiley."},{"key":"252_CR4","doi-asserted-by":"crossref","unstructured":"Spagna, F. (2001) An improved delay compensation technique for digital clock recovery loops\u201d. The 8th IEEE International Conference on Electronics, Circuits and Systems (ICECS), vol. 3, pp. 1395\u20131398.","DOI":"10.1109\/ICECS.2001.957475"},{"issue":"4","key":"252_CR5","doi-asserted-by":"crossref","first-page":"229","DOI":"10.1109\/81.382480","volume":"42","author":"J. W. M. Bergmans","year":"1995","unstructured":"Bergmans, J. W. M. (1995). Effect of loop delay on stability of discrete-time PLL. IEEE Transactions on Circuits and Systems-I, 42(4), 229\u2013231, (April).","journal-title":"IEEE Transactions on Circuits and Systems-I"},{"issue":"8","key":"252_CR6","doi-asserted-by":"crossref","first-page":"1026","DOI":"10.1109\/81.780384","volume":"46","author":"A. Gloria De","year":"1999","unstructured":"De Gloria, A., Grosso, D., Olivieri, M., & Restani, G. (1999). A novel stability analysis of a PLL for timing recovery in hard disk drives. IEEE Transactions on Circuits and Systems-I, 46(8), 1026\u20131031, (August).","journal-title":"IEEE Transactions on Circuits and Systems-I"},{"key":"252_CR7","volume-title":"Digital communications receivers. synchronization, chanel estimation and signal processing","author":"H. Meyr","year":"1998","unstructured":"Meyr, H., Moeneclaey, M., & Fechtel, S. A. (1998). Digital communications receivers. synchronization, chanel estimation and signal processing. New York: Wiley."},{"issue":"5","key":"252_CR8","doi-asserted-by":"crossref","first-page":"423","DOI":"10.1109\/TCOM.1986.1096561","volume":"COM-34","author":"F. M. Gardner","year":"1986","unstructured":"Gardner, F. M. (1986). A BPSK\/QPSK timing-error detector for sampled receivers. IEEE Transactions on Communications, COM-34(5), 423\u2013429, (May).","journal-title":"IEEE Transactions on Communications"},{"key":"252_CR9","doi-asserted-by":"crossref","unstructured":"Cardells, F., Valls J., Almenar, V. (2003). Symbol timing synchronization in FPGA-based software radios: Application to DVB-S. 13th International Conference on Field Programmable Logic and Applications (FPL 2003), Lisbon, Portugal, September.","DOI":"10.1007\/978-3-540-45234-8_4"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0252-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-008-0252-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0252-0","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T08:19:29Z","timestamp":1559377169000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-008-0252-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7,12]]},"references-count":9,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2009,7]]}},"alternative-id":["252"],"URL":"https:\/\/doi.org\/10.1007\/s11265-008-0252-0","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,7,12]]}}}