{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,6]],"date-time":"2025-12-06T16:56:16Z","timestamp":1765040176811},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2008,7,31]],"date-time":"2008-07-31T00:00:00Z","timestamp":1217462400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2009,7]]},"DOI":"10.1007\/s11265-008-0253-z","type":"journal-article","created":{"date-parts":[[2008,7,30]],"date-time":"2008-07-30T19:03:09Z","timestamp":1217444589000},"page":"25-33","source":"Crossref","is-referenced-by-count":9,"title":["Low-Power FPGA-Implementation of atan(Y\/X) Using Look-Up Table Methods for Communication Applications"],"prefix":"10.1007","volume":"56","author":[{"given":"R.","family":"Gutierrez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"J.","family":"Valls","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,7,31]]},"reference":[{"key":"253_CR1","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4899-1807-9","volume-title":"Synchronization techniques for digital receivers","author":"U. Mengali","year":"1997","unstructured":"Mengali, U., & D\u2019Andrea, A. N. (1997). Synchronization techniques for digital receivers. Berlin: Springer."},{"key":"253_CR2","volume-title":"OFDM wireless LANs. A theoretical and practical guide","author":"J. Heiskala","year":"2001","unstructured":"Heiskala, J., & Terry, J. (2001). OFDM wireless LANs. A theoretical and practical guide. Indianapolis, IN: Sams."},{"key":"253_CR3","doi-asserted-by":"crossref","first-page":"181","DOI":"10.1007\/s11265-007-0146-6","volume":"52","author":"F. Angarita","year":"2008","unstructured":"Angarita, F., Canet, M. J., Sansaloni, T., Perez-Pascual, A., & Valls, J. (2008). Efficient mapping of CORDIC algorithm for OFDM-based WLAN. Journal of Signal Processing Systems, 52, 181\u2013191.","journal-title":"Journal of Signal Processing Systems"},{"key":"253_CR4","doi-asserted-by":"crossref","unstructured":"Canet, M. J., Vicedo, F., Almenar, V., & Valls, J. (2004). FPGA implementation of an IF transceiver for OFDM-based WLAN. 2004 IEEE Workshop on Signal Processing Systems (SiPS 2004), pp. 227\u2013232, August, Austin, Texas.","DOI":"10.1109\/SIPS.2004.1363054"},{"key":"253_CR5","volume-title":"Computer arithmetic. Algorithms and hardware design","author":"B. Parhami","year":"2000","unstructured":"Parhami, B. (2000). Computer arithmetic. Algorithms and hardware design. New York: Oxford University Press."},{"key":"253_CR6","doi-asserted-by":"crossref","unstructured":"Story, S., & Tang, P. T. P. (1999). New algorithms for improved transcendental functions on IA-64. arith, p. 4, 14th IEEE Symposium on Computer Arithmetic (ARITH-14 \u201999).","DOI":"10.1109\/ARITH.1999.762822"},{"key":"253_CR7","volume-title":"Elementary functions. Algorithms and implementation","author":"J.-M. Muller","year":"2006","unstructured":"Muller, J.-M. (2006). Elementary functions. Algorithms and implementation. New York: Birkha\u00fcser Boston."},{"issue":"8","key":"253_CR8","doi-asserted-by":"crossref","first-page":"964","DOI":"10.1109\/12.295858","volume":"43","author":"M. J. Schulte","year":"1994","unstructured":"Schulte, M. J., & Swartzlander, E. E. (1994). Hardware designs for exactly rounded elementary functions. IEEE Transactions on Computers, 43(8), 964\u2013973. doi: 10.1109\/12.295858 .","journal-title":"IEEE Transactions on Computers"},{"key":"253_CR9","doi-asserted-by":"crossref","unstructured":"Ferguson, W. (1995). Exact computation of a sum or difference with applications to argument reduction. IEEE Symposium on Computer Arithmetic, pp. 216\u2013221.","DOI":"10.1109\/ARITH.1995.465355"},{"key":"253_CR10","doi-asserted-by":"crossref","unstructured":"Das Sarma, D., & Matula, D. W. (1997). Faithful interpolation in reciprocal tables. IEEE Symposium on Computer Arithmetic, pp. 82\u201391.","DOI":"10.1109\/ARITH.1997.614882"},{"key":"253_CR11","doi-asserted-by":"crossref","unstructured":"Das Sarma, D., & Matula, D. W. (1995). Faithful bipartite ROM reciprocal tables. IEEE Symposium on Computer Arithmetic, pp. 17.","DOI":"10.1109\/ARITH.1995.465381"},{"key":"253_CR12","doi-asserted-by":"crossref","unstructured":"Shulte, M. J., & Stine, J. E. (1997). Symmetric bipartite tables for accurate function approximation. Proceeding of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, pp. 144\u2013153, IEEE Computer Society Press.","DOI":"10.1109\/ASAP.1997.606821"},{"key":"253_CR13","doi-asserted-by":"crossref","unstructured":"de Dinechin, F., & Tisserand, A. (2001). Some improvements on multipartite table methods. IEEE Symposium on Computer Arithmetic, pp. 128\u2013135.","DOI":"10.1109\/ARITH.2001.930112"},{"key":"253_CR14","doi-asserted-by":"crossref","unstructured":"Cao, J., We, B. W. Y., & Cheng, J. (2001). High-performance architectures for elementary function generation. IEEE Symposium on Computer Arithmetic, pp. 136\u2013144.","DOI":"10.1109\/ARITH.2001.930113"},{"issue":"6","key":"253_CR15","doi-asserted-by":"crossref","first-page":"863","DOI":"10.1109\/PGEC.1965.264080","volume":"EC-14","author":"M. Combet","year":"1965","unstructured":"Combet, M., Van Zonneveld, H., & Verbeek, L. (1965). Computation of the base two logarithm of binary numbers. IEEE Transactions on Electronics Computers, EC-14(6), 863\u2013867.","journal-title":"IEEE Transactions on Electronics Computers"},{"key":"253_CR16","doi-asserted-by":"crossref","unstructured":"Lee, D. U., Luk, W., Villasenor, J., & Cheung, P. Y. K. (2003). Hierarchical segmentation schemes for function evaluation. Proceeding of IEEE International Conference on Field-Programmable Technology, pp. 92\u201399.","DOI":"10.1109\/FPT.2003.1275736"},{"issue":"1","key":"253_CR17","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1109\/92.273153","volume":"2","author":"V. G. Oklobdzija","year":"1994","unstructured":"Oklobdzija, V. G. (1994). An algorithmic and novel design of a leading zero detector circuit. Comparison with logic synthesis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2(1), 124\u2013128.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0253-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-008-0253-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0253-z","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T12:19:29Z","timestamp":1559391569000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-008-0253-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,7,31]]},"references-count":17,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2009,7]]}},"alternative-id":["253"],"URL":"https:\/\/doi.org\/10.1007\/s11265-008-0253-z","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,7,31]]}}}