{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,21]],"date-time":"2025-12-21T06:23:55Z","timestamp":1766298235723},"reference-count":52,"publisher":"Springer Science and Business Media LLC","issue":"2","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2009,11]]},"DOI":"10.1007\/s11265-008-0256-9","type":"journal-article","created":{"date-parts":[[2008,8,11]],"date-time":"2008-08-11T15:48:19Z","timestamp":1218469699000},"page":"173-194","source":"Crossref","is-referenced-by-count":53,"title":["Parallel Scalability of Video Decoders"],"prefix":"10.1007","volume":"57","author":[{"given":"Cor","family":"Meenderinck","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arnaldo","family":"Azevedo","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ben","family":"Juurlink","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mauricio","family":"Alvarez Mesa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alex","family":"Ramirez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2008,8,12]]},"reference":[{"key":"256_CR1","unstructured":"ClearSpeed (2008) The CSX600 processor. [Online]. http:\/\/www.clearspeed.com ."},{"key":"256_CR2","unstructured":"Tilera (2007) TILE64(TM) processor family. [Online]. http:\/\/www.tilera.com ."},{"key":"256_CR3","doi-asserted-by":"crossref","unstructured":"Stenstr\u00f6m, P. (2006). Chip-multiprocessing and beyond. In Proc. twelfth int. symp. on high-performance computer architecture (pp. 109\u2013109).","DOI":"10.1109\/HPCA.2006.1598117"},{"key":"256_CR4","unstructured":"Asanovic, K., et al. (2006). The landscape of parallel computing research: A view from Berkeley. EECS Department University of California, Berkeley, Tech. Rep. UCB\/EECS-2006-183, December."},{"key":"256_CR5","unstructured":"Liao, H., & Wolfe, A. (1997) Available parallelism in video applications. In Proc. 30th annual int. symp. on microarchitecture (Micro \u201997)."},{"key":"256_CR6","doi-asserted-by":"crossref","unstructured":"Kissell, K. (2008). MIPS MT: A multithreaded RISC architecture for embedded real-time processing. In Proc. high performance embedded architectures and compilers (HiPEAC) conference.","DOI":"10.1007\/978-3-540-77560-7_2"},{"key":"256_CR7","unstructured":"Oelbaum, T., Baroncini, V., Tan, T., & Fenimore, C. (2004). Subjective quality assessment of the emerging AVC\/H.264 video coding standard. In Int. broadcast conference (IBC)."},{"key":"256_CR8","unstructured":"International Standard of Joint Video Specification (ITU-T Rec. H. 264| ISO\/IEC 14496-10 AVC) (2005)."},{"issue":"7","key":"256_CR9","doi-asserted-by":"crossref","first-page":"587","DOI":"10.1109\/TCSVT.2003.814963","volume":"13","author":"M. Flierl","year":"2003","unstructured":"Flierl, M., & Girod, B. (2003). Generalized B pictures and the draft H. 264\/AVC video-compression standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 587\u2013597.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR10","doi-asserted-by":"crossref","first-page":"560","DOI":"10.1109\/TCSVT.2003.815165","volume":"13","author":"T. Wiegand","year":"2003","unstructured":"Wiegand, T., Sullivan, G. J., Bjontegaard, G., & A.Luthra (2003). Overview of the H.264\/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560\u2013576, July.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"256_CR11","unstructured":"Tamhankar, A., & Rao, K. (2003). An overview of H. 264\/MPEG-4 Part 10. In Proc. 4th EURASIP conference focused on video\/image processing and multimedia communications (p. 1)."},{"issue":"7","key":"256_CR12","doi-asserted-by":"crossref","first-page":"598","DOI":"10.1109\/TCSVT.2003.814964","volume":"13","author":"H. Malvar","year":"2003","unstructured":"Malvar, H., Hallapuro, A., Karczewicz, M., & Kerofsky, L. (2003). Low-complexity transform and quantization in H. 264\/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 598\u2013603.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR13","doi-asserted-by":"crossref","first-page":"604","DOI":"10.1109\/TCSVT.2003.815380","volume":"13","author":"M. Wien","year":"2003","unstructured":"Wien, M. (2003). Variable block-size transforms for H. 264\/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 604\u2013613.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR14","doi-asserted-by":"crossref","first-page":"614","DOI":"10.1109\/TCSVT.2003.815175","volume":"13","author":"P. List","year":"2003","unstructured":"List, P., Joch, A., Lainema, J., Bjntegaard, G., & Karczewicz, M. (2003). Adaptive deblocking filter. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 614\u2013619.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR15","doi-asserted-by":"crossref","first-page":"620","DOI":"10.1109\/TCSVT.2003.815173","volume":"13","author":"D. Marpe","year":"2003","unstructured":"Marpe, D., Schwarz, H., & Wiegand, T. (2003). Context-based adaptive binary arithmetic coding in the H.264\/AVC video compression standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 620\u2013636.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"256_CR16","doi-asserted-by":"crossref","unstructured":"Sullivan, G., Topiwala, P., & Luthra, A. (2004). The H.264\/AVC advanced video coding standard: Overview and introduction to the fidelity range extensions. In Proc. SPIE conference on applications of digital image processing XXVII (pp. 454\u2013474).","DOI":"10.1117\/12.564457"},{"key":"256_CR17","unstructured":"Alvarez, M., Salami, E., Ramirez, A., & Valero, M. (2007). HD-VideoBench: A benchmark for evaluating high definition digital video applications. In IEEE int. symp. on workload characterization, [Online]. http:\/\/personals.ac.upc.edu\/alvarez\/hdvideobench\/index.html ."},{"key":"256_CR18","unstructured":"X264 (2008). A free H.264\/AVC encoder. [Online]. http:\/\/developers.videolan.org\/x264.html ."},{"key":"256_CR19","unstructured":"FFmpeg (2008). The FFmpeg Libavcoded [Online]. http:\/\/ffmpeg.mplayerhq.hu\/ ."},{"key":"256_CR20","doi-asserted-by":"crossref","unstructured":"Alvarez, M., Salami, E., Ramirez, A., & Valero, M. (2005). A performance characterization of high definition digital video decoding using H.264\/AVC. In Proc. IEEE int. workload characterization symposium (pp. 24\u201333).","DOI":"10.1109\/IISWC.2005.1525998"},{"issue":"1","key":"256_CR21","doi-asserted-by":"crossref","first-page":"7","DOI":"10.1109\/MCAS.2004.1286980","volume":"4","author":"J. Ostermann","year":"2004","unstructured":"Ostermann, J., Bormans, J., List, P., Marpe, D., Narroschke, M., Pereira, F., et al. (2004). Video coding with H.264\/AVC: Tools, performance, and complexity. IEEE Circuits and Systems Magazine, 4(1), 7\u201328.","journal-title":"IEEE Circuits and Systems Magazine"},{"issue":"7","key":"256_CR22","doi-asserted-by":"crossref","first-page":"717","DOI":"10.1109\/TCSVT.2003.814968","volume":"13","author":"V. Lappalainen","year":"2003","unstructured":"Lappalainen, V., Hallapuro, A., & Hamalainen, T. D. (2003). Complexity of optimized H.26L video decoder implementation. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 717\u2013725.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR23","doi-asserted-by":"crossref","first-page":"704","DOI":"10.1109\/TCSVT.2003.814967","volume":"13","author":"M. Horowitz","year":"2003","unstructured":"Horowitz, M., Joch, A., & Kossentini, F. (2003). H.264\/AVC baseline profile decoder complexity analyis. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 704\u2013716.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"7","key":"256_CR24","doi-asserted-by":"crossref","first-page":"587","DOI":"10.1109\/TCSVT.2003.814963","volume":"13","author":"M. Flierl","year":"2003","unstructured":"Flierl, M., & Girod, B. (2003). Generalized B pictures and the draft H.264\/AVC video-compression standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 587\u2013597, July.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"256_CR25","unstructured":"Zhou, X., Li, E. Q., & Chen, Y.-K. (2003). Implementation of H.264 decoder on general-purpose processors with media instructions. In Proc. SPIE conf. on image and video communications and processing."},{"key":"256_CR26","unstructured":"Shojania, H., Sudharsanan, S., & Wai-Yip, C., (2006). Performance improvement of the h.264\/avc deblocking filter using simd instructions. In Proc. IEEE int. symp. on circuits and systems ISCAS, May."},{"key":"256_CR27","unstructured":"Lee, J., Moon, S., & Sung, W. (2004). H.264 decoder optimization exploiting SIMD instructions. In Asia-Pacific conf. on circuits and systems, Dec."},{"key":"256_CR28","doi-asserted-by":"crossref","unstructured":"Zhao, Z., & Liang, P. (2006). Data partition for wavefront parallelization of H.264 video encoder. In IEEE international symposium on circuits and systems, ISCAS 2006, 21\u201324 May.","DOI":"10.1109\/ISCAS.2006.1693173"},{"key":"256_CR29","doi-asserted-by":"crossref","unstructured":"Schaumont, P., Lai, B.-C. C., Qin, W., & Verbauwhede, I. (2005). Cooperative multithreading on embedded multiprocessor architectures enables energy-scalable design. In DAC \u201905: Proceedings of the 42nd annual conference on design automation (pp. 27\u201330).","DOI":"10.1109\/DAC.2005.193767"},{"key":"256_CR30","doi-asserted-by":"crossref","unstructured":"Tian, X., Chen, Y.-K., Girkar, M., Ge, S., Lienhart, R., & Shah, S. (2003). Exploring the use of hyper-threading technology for multimedia applications with intel openmp compiler. In Proceedings of the international parallel and distributed processing symposium, 2003, 22\u201326 April.","DOI":"10.1109\/IPDPS.2003.1213118"},{"key":"256_CR31","unstructured":"Ayguad\u00e9, E., Copty, N., Duran, A., Hoeflinger, J., Lin, Y., Massaioli, F., et al. (2007). A proposal for task parallelism in OpenMP. In Proceedings of the 3rd international workshop on OpenMP, June."},{"key":"256_CR32","unstructured":"X264-devel \u2013 Mailing list for \u00d7264 developers (2007). Subject: Out-of-range motion vectors. [Online]. http:\/\/mailman.videolan.org\/listinfo\/\u00d7264-devel , July\u2013August."},{"key":"256_CR33","unstructured":"Shen, K., Rowe, L. A., & Delp, E. J. (1995). Parallel implementation of an MPEG-1 encoder: Faster than real time. In Proc. SPIE, digital video compression: Algorithms and technologies 1995 (Vol. 2419, pp. 407\u2013418)."},{"key":"256_CR34","doi-asserted-by":"crossref","unstructured":"Bilas, A., Fritts, J., & Singh, J. (1997). Real-time parallel mpeg-2 decoding in software. In Parallel processing symposium, 1997. Proceedings., 11th international (pp. 197\u2013203), 1\u20135 April.","DOI":"10.1109\/IPPS.1997.580889"},{"issue":"4","key":"256_CR35","doi-asserted-by":"crossref","first-page":"687","DOI":"10.1109\/76.611179","volume":"7","author":"S. Akramullah","year":"1997","unstructured":"Akramullah, S., Ahmad, I., & Liou, M. (1997). Performance of software-based mpeg-2 video encoder on parallel and distributed systems. IEEE Transactions on Circuits and Systems for Video Technology, 7(4), 687\u2013695, August.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"256_CR36","doi-asserted-by":"crossref","unstructured":"Taylor, H., Chin, D., & Jessup, A. (1993). A mpeg encoder implementation on the princeton engine video supercomputer. In Data compression conference, 1993. DCC \u201993. (pp. 420\u2013429).","DOI":"10.1109\/DCC.1993.253107"},{"key":"256_CR37","unstructured":"Lehtoranta, O., Hamalainen, T., & Saarinen, J. (2001). Parallel implementation of h.263 encoder for cif-sized images on quad dsp system. In The 2001 IEEE international symposium on circuits and systems, ISCAS 2001 (Vol. 2, pp. 209\u2013212), 6\u20139 May."},{"key":"256_CR38","doi-asserted-by":"crossref","unstructured":"Lee, C., Ho, C. S., Tsai, S.-F., Wu, C.-F., Cheng, J.-Y., Wang, L.-W., et al. (1996). Implementation of digital hdtv video decoder by multiple multimedia video processors. In International conference on consumer electronics, 1996 (pp. 98\u2013), 5\u20137 June.","DOI":"10.1109\/ICCE.1996.517225"},{"key":"256_CR39","doi-asserted-by":"crossref","unstructured":"Lin, W., Goh, K., Tye, B., Powell, G., Ohya, T., & Adachi, S. (1997). Real time h.263 video codec using parallel dsp. In International Conference on Image Processing, 1997 (Vol. 2, pp. 586\u2013589), 26\u201329 October.","DOI":"10.1109\/ICIP.1997.638839"},{"key":"256_CR40","doi-asserted-by":"crossref","unstructured":"Cantineau, O., & Legat, J.-D. (1998). Efficient parallelisation of an mpeg-2 codec on a tms320c80 video processor. In 1998 international conference on image processing, 1998. ICIP 98 (Vol. 3, pp. 977\u2013980), 4\u20137 October.","DOI":"10.1109\/ICIP.1998.727413"},{"key":"256_CR41","doi-asserted-by":"crossref","unstructured":"Oehring, H., Sigmund, U., & Ungerer, T. (1999). Mpeg-2 video decompression on simultaneous multithreaded multimedia processors. In International conference on parallel architectures and compilation techniques, 1999 (pp. 11\u201316).","DOI":"10.1109\/PACT.1999.807400"},{"key":"256_CR42","doi-asserted-by":"crossref","unstructured":"Ganesh Yadav, R. S., & Chaudhary, V. (2004). On implementation of MPEG-2 like real-time parallel media applications on MDSP SoC cradle architecture. In Lecture notes in computer science. Embedded and ubiquitous computing, July.","DOI":"10.1007\/978-3-540-30121-9_27"},{"issue":"1","key":"256_CR43","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1109\/TCE.2006.1605057","volume":"52","author":"T. Jacobs","year":"2006","unstructured":"Jacobs, T., Chouliaras, V., & Mulvaney, D. (2006). Thread-parallel mpeg-2, mpeg-4 and h.264 video encoders for soc multi-processor architectures. IEEE Transactions on Consumer Electronics, 52(1), 269\u2013275, February.","journal-title":"IEEE Transactions on Consumer Electronics"},{"key":"256_CR44","unstructured":"Gulati, A., & Campbell, G. (2005). Efficient mapping of the H.264 encoding algorithm onto multiprocessor DSPs. In Proc. embedded processors for multimedia and communications II, 5683(1), 94\u2013103, March."},{"key":"256_CR45","doi-asserted-by":"crossref","unstructured":"Klaus Sch\u00f6ffmann, O. L., Fauster, M., & B\u00f6sz\u00f6rmenyi, L. (2007). An evaluation of parallelization concepts for baseline-profile compliant H.264\/AVC decoders. In Lecture notes in computer science. Euro-Par 2007 parallel processing, August.","DOI":"10.1007\/978-3-540-74466-5_83"},{"key":"256_CR46","doi-asserted-by":"crossref","unstructured":"Rodriguez, A., Gonzalez, A., & Malumbres, M. P. (2006). Hierarchical parallelization of an h.264\/avc video encoder. In Proc. int. symp. on parallel computing in electrical engineering (pp. 363\u2013368).","DOI":"10.1109\/PARELEC.2006.42"},{"key":"256_CR47","unstructured":"Chen, Y., Tian, X., Ge, S., & Girkar, M. (2004). Towards efficient multi-level threading of h.264 encoder on intel hyper-threading architectures. In Proc. 18th int. parallel and distributed processing symposium."},{"key":"256_CR48","unstructured":"Roitzsch, M. (2006). Slice-balancing H.264 video encoding for improved scalability of multicore decoding. In Work-in-progress proc. 27th IEEE real-time systems symposium."},{"key":"256_CR49","unstructured":"van der Tol, E., Jaspers, E., & Gelderblom, R. (2003). Mapping of H.264 decoding on a multiprocessor architecture. In Proc. SPIE conf. on image and video communications and processing."},{"key":"256_CR50","doi-asserted-by":"crossref","first-page":"509","DOI":"10.1016\/j.jvcir.2005.05.004","volume":"17","author":"Y. Chen","year":"2006","unstructured":"Chen, Y., Li, E., Zhou, X., & Ge, S. (2006). Implementation of H. 264 encoder and decoder on personal computers. Journal of Visual Communications and Image Representation, 17, 509\u2013532.","journal-title":"Journal of Visual Communications and Image Representation"},{"key":"256_CR51","unstructured":"Intel Integrated Performance Primitives (2008). [Online]. http:\/\/www.intel.com\/cd\/software\/products\/asmo-na\/eng\/perflib\/ipp\/302910.htm ."},{"key":"256_CR52","unstructured":"Chong, J., Satish, N. R., Catanzaro, B., Ravindran, K., & Keutzer, K. (2007). Efficient parallelization of h.264 decoding with macro block level scheduling. In 2007 IEEE international conference on multimedia and expo (pp. 1874\u20131877), July."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0256-9.pdf","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,18]],"date-time":"2019-04-18T14:52:28Z","timestamp":1555599148000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-008-0256-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,8,12]]},"references-count":52,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2009,11]]}},"alternative-id":["256"],"URL":"https:\/\/doi.org\/10.1007\/s11265-008-0256-9","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2008,8,12]]}}}