{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,2]],"date-time":"2025-02-02T05:34:08Z","timestamp":1738474448212,"version":"3.35.0"},"reference-count":27,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2008,10,16]],"date-time":"2008-10-16T00:00:00Z","timestamp":1224115200000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst Sign Image Video Technol"],"published-print":{"date-parts":[[2010,4]]},"DOI":"10.1007\/s11265-008-0286-3","type":"journal-article","created":{"date-parts":[[2008,10,15]],"date-time":"2008-10-15T18:13:44Z","timestamp":1224094424000},"page":"45-55","source":"Crossref","is-referenced-by-count":2,"title":["Compiling for Reduced Bit-Width Queue Processors"],"prefix":"10.1007","volume":"59","author":[{"given":"Arquimedes","family":"Canedo","sequence":"first","affiliation":[]},{"given":"Ben A.","family":"Abderazek","sequence":"additional","affiliation":[]},{"given":"Masahiro","family":"Sowa","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2008,10,16]]},"reference":[{"key":"286_CR1","doi-asserted-by":"crossref","unstructured":"Goudge, L., & Segars, S. (1996). Thumb: Reducing the cost of 32-bit RISC performance in portable and consumer applications. In Proceedings of COMPCON \u201996 (pp. 176\u2013181).","DOI":"10.1109\/CMPCON.1996.501765"},{"key":"286_CR2","unstructured":"Kissel, K. (1997). MIPS16: High-density MIPS for the embedded market. Technical report, Silicon Graphics MIPS Group."},{"key":"286_CR3","unstructured":"Renesas (2008). SuperH RISC Engine. http:\/\/www.superh.com ."},{"key":"286_CR4","volume-title":"Stack computers: The new wave","author":"P.J. Koopman","year":"1989","unstructured":"Koopman, P.J. (1989). Stack computers: The new wave. Chichester: Ellis Horwood."},{"issue":"10","key":"286_CR5","doi-asserted-by":"crossref","first-page":"22","DOI":"10.1109\/2.722273","volume":"31","author":"H. McGhan","year":"1998","unstructured":"McGhan, H., & O\u2019Connor, M. (1998). Picojava: A direct execution engine for java bytecode. Computer, 31(10), 22\u201330.","journal-title":"Computer"},{"key":"286_CR6","unstructured":"Vijaykrishnan, N. (1998). Issues in the design of a Java processor architecture. PhD thesis, University of South Florida."},{"key":"286_CR7","doi-asserted-by":"crossref","unstructured":"Kucuk, G., Ergin, O., Ponomarev, D., & Ghose, K. (2003). Energy efficient register renaming. In Lecture notes in computer science (vol. 2799\/2003, pp. 219\u2013228), September.","DOI":"10.1007\/978-3-540-39762-5_28"},{"key":"286_CR8","doi-asserted-by":"crossref","unstructured":"Krishnaswamy, A., & Gupta, R. (2002). Profile guided selection of ARM and Thumb instructions. In ACM SIGPLAN conference on languages, compilers, and tools for embedded systems (pp. 56\u201364).","DOI":"10.1145\/513829.513840"},{"key":"286_CR9","doi-asserted-by":"crossref","unstructured":"Halambi, A., Shrivastava, A., Biswas, P., Dutt, N., & Nicolau, A. (2002). An efficient compiler technique for code size reduction using reduced bit-width ISAs. In Proceedings of the conference on design, automation and test in Europe (p. 402).","DOI":"10.1109\/DATE.2002.998305"},{"key":"286_CR10","first-page":"33","volume-title":"Lectures in computer science","author":"L. Sheayun","year":"2003","unstructured":"Sheayun, L., Jaejin, L., & Min, S. (2003). Code generation for a dual instruction processor based on selective code transformation. In Lectures in computer science (pp. 33\u201348). New York: Springer."},{"key":"286_CR11","doi-asserted-by":"crossref","first-page":"2098","DOI":"10.1049\/el:19991420","volume":"35","author":"Y. Kwon","year":"1999","unstructured":"Kwon, Y., Ma, X., & Lee, H.J. (1999). Pare: Instruction set architecture for efficient code size reduction. Electronics Letters, 35, 2098\u20132099.","journal-title":"Electronics Letters"},{"key":"286_CR12","doi-asserted-by":"crossref","unstructured":"Krishnaswamy, A., & Gupta, R. (2003). Enhancing the performance of 16-bit code using augmenting instructions. In Proceedings of the 2003 SIGPLAN conference on language, compiler, and tools for embedded systems (pp. 254\u2013264).","DOI":"10.1145\/780732.780767"},{"key":"286_CR13","unstructured":"Krishnaswamy, A. (2006). Microarchitecture and compiler techniques for dual width ISA processors. PhD thesis, University of Arizona, September."},{"issue":"3","key":"286_CR14","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1007\/s11227-005-0160-z","volume":"32","author":"M. Sowa","year":"2005","unstructured":"Sowa, M., Abderazek, B., & Yoshinaga, T. (2005). Parallel queue processor architecture based on produced order computation model. Journal of Supercomputing, 32(3), 217\u2013229, June.","journal-title":"Journal of Supercomputing"},{"issue":"1","key":"286_CR15","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1007\/s11227-006-6719-5","volume":"38","author":"B. Abderazek","year":"2006","unstructured":"Abderazek, B., Yoshinaga, T., & Sowa, M. (2006). High-level modeling and FPGA prototyping of produced order parallel queue processor core. Journal of Supercomputing, 38(1), 3\u201315, October.","journal-title":"Journal of Supercomputing"},{"issue":"2","key":"286_CR16","doi-asserted-by":"crossref","first-page":"191","DOI":"10.3233\/EMC-2006-00028","volume":"2","author":"B. Abderazek","year":"2006","unstructured":"Abderazek, B., Kawata, S., & Sowa, M. (2006). Design and architecture for an embedded 32-bit QueueCore. Journal of Embedded Computing, 2(2), 191\u2013205.","journal-title":"Journal of Embedded Computing"},{"key":"286_CR17","unstructured":"Canedo, A. (2006). Code generation algorithms for consumed and produced order queue machines. Master\u2019s thesis, Tokyo, Japan: University of Electro-Communications, September."},{"key":"286_CR18","doi-asserted-by":"crossref","unstructured":"Preiss, B., & Hamacher, C. (1985). Data flow on queue machines. In 12th Int. IEEE symposium on computer architecture (pp. 342\u2013351).","DOI":"10.1145\/327070.327367"},{"issue":"4","key":"286_CR19","doi-asserted-by":"crossref","first-page":"184","DOI":"10.1016\/j.cl.2007.06.003","volume":"34","author":"A. Canedo","year":"2007","unstructured":"Canedo, A., Abderazek, B., & Sowa, M. (2007). A new code generation algorithm for 2-offset producer order queue computation model. Journal of Computer Languages, Systems & Structures, 34(4), 184\u2013194, June.","journal-title":"Journal of Computer Languages, Systems & Structures"},{"key":"286_CR20","unstructured":"Merrill, J. (2003). GENERIC and GIMPLE: A new tree representation for entire functions. In Proceedings of GCC developers summit (pp. 171\u2013180)."},{"key":"286_CR21","unstructured":"Novillo, D. (2004). Design and implementation of tree SSA. In Proceedings of GCC Developers Summit (pp. 119\u2013130)."},{"issue":"4","key":"286_CR22","doi-asserted-by":"crossref","first-page":"1510","DOI":"10.1137\/S0097539795280287","volume":"28","author":"L.S. Heath","year":"1999","unstructured":"Heath, L.S., & Pemmaraju, S.V. (1999). Stack and queue layouts of directed acyclic graphs: part I. SIAM Journal on Computing, 28(4) 1510\u20131539.","journal-title":"SIAM Journal on Computing"},{"issue":"3","key":"286_CR23","doi-asserted-by":"crossref","first-page":"2","DOI":"10.1145\/306225.306228","volume":"26","author":"J.J. Dujmovic","year":"1998","unstructured":"Dujmovic, J.J., & Dujmovic, I. (1998). Evolution and evaluation of SPEC benchmarks. ACM SIGMETRICS Performance Evaluation Review, 26(3), 2\u20139, December.","journal-title":"ACM SIGMETRICS Performance Evaluation Review"},{"key":"286_CR24","volume-title":"Compilers principles, techniques, and tools","author":"A.V. Aho","year":"1986","unstructured":"Aho, A.V., Sethi, R., & Ullman, J.D. (1986). Compilers principles, techniques, and tools. Redwood City: Addison Wesley."},{"key":"286_CR25","volume-title":"Advanced compiler design and implementation","author":"S.S. Muchnick","year":"1997","unstructured":"Muchnick, S.S. (1997) Advanced compiler design and implementation. San Francisco: Morgan Kaufman."},{"key":"286_CR26","doi-asserted-by":"crossref","unstructured":"Canedo, A., Abderazek, B., & Sowa, M. (2008). Quantitative evaluation of common subexpression elimination on queue machines. In Proceedings of the international symposium on parallel architectures, algorithms, and networks (I-SPAN 2008) (pp. 25\u201330).","DOI":"10.1109\/I-SPAN.2008.25"},{"key":"286_CR27","volume-title":"MIPS RISC architecture","author":"G. Kane","year":"1992","unstructured":"Kane, G., & Heinrich, J. (1992). MIPS RISC architecture. Englewood Cliffs: Prentice Hall."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0286-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-008-0286-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-008-0286-3","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T22:23:55Z","timestamp":1738448635000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-008-0286-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2008,10,16]]},"references-count":27,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2010,4]]}},"alternative-id":["286"],"URL":"https:\/\/doi.org\/10.1007\/s11265-008-0286-3","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2008,10,16]]}}}