{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2023,9,12]],"date-time":"2023-09-12T16:48:26Z","timestamp":1694537306043},"reference-count":25,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2010,4,20]],"date-time":"2010-04-20T00:00:00Z","timestamp":1271721600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1007\/s11265-010-0470-0","type":"journal-article","created":{"date-parts":[[2010,4,19]],"date-time":"2010-04-19T13:36:40Z","timestamp":1271684200000},"page":"373-382","source":"Crossref","is-referenced-by-count":12,"title":["Parallel Architecture Core (PAC)\u2014the First Multicore Application Processor SoC in Taiwan Part I: Hardware Architecture &amp; Software Development Tools"],"prefix":"10.1007","volume":"62","author":[{"given":"David Chih-Wei","family":"Chang","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tay-Jyi","family":"Lin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chung-Ju","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jenq-Kuen","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yuan-Hua","family":"Chu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"An-Yeu","family":"Wu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2010,4,20]]},"reference":[{"key":"470_CR1","unstructured":"Lin, T. J., Liu, C. N., Tseng, S. Y., Chu, Y. H., & Wu, A. Y. (2008). Overview of ITRI PAC project\u2014from VLIW DSP processor to multicore computing platform. In Proc. VLSI-DAT, Apr. 2008, pp.188\u2013191."},{"key":"470_CR2","unstructured":"Chang, C. W. et al. (2006). PACDSP core and application processors. In Proc. ICME, July 2006, pp.289\u2013292."},{"key":"470_CR3","doi-asserted-by":"crossref","first-page":"209","DOI":"10.1007\/s11265-007-0061-x","volume":"51","author":"TJ Lin","year":"2008","unstructured":"Lin, T. J., Hsiao, P. C., Chen, S. K., Kuo, Y. T., & Liu, C. W. (2008). Design & implementation of a high-performance & complexity-effective VLIW DSP for multimedia applications. Journal of Signal Processing Systems, 51, 209\u2013223.","journal-title":"Journal of Signal Processing Systems"},{"key":"470_CR4","unstructured":"http:\/\/www.itri.org.tw\/"},{"key":"470_CR5","unstructured":"Lapsley, P., Bier, J., & Lee, E. A. (1996). DSP Processor fundamentals\u2014architectures and features. IEEE Press."},{"key":"470_CR6","unstructured":"Hu, Y. H. (2002). Programmable digital signal processors\u2014architecture, programming, and applications. Marcel Dekker Inc."},{"key":"470_CR7","unstructured":"Fisher, J. A., Faraboschi, P., & Young, C. (2005). Embedded computing\u2014A VLIW approach to architecture, compiler, and tools. Morgan Kaufmann."},{"key":"470_CR8","first-page":"117","volume":"13","author":"TJ Lin","year":"2006","unstructured":"Lin, T. J., Hsiao, P. C., Liu, C. W., & Jen, C. W. (2006). Area-efficient register organization for fully-synthesizable VLIW DSP cores. International Journal of Electrical Engineering, 13, 117\u2013127.","journal-title":"International Journal of Electrical Engineering"},{"key":"470_CR9","unstructured":"Lin, T. J., Lee, C. C., Liu, C. W., & Jen, C. W. (2005). A novel register organization for VLIW digital signal processors. In Proc. VLSI-TSA-DAT, Apr. 2005, pp.337\u2013340."},{"key":"470_CR10","unstructured":"http:\/\/www.bdti.com\/bdtimark\/core_scores.pdf"},{"key":"470_CR11","doi-asserted-by":"crossref","unstructured":"Lin, T. J. et al. (2005). A unified processor architecture for RISC & VLIW DSP. In Proc. GLSVLSI, Apr. 2005, pp.50\u201355.","DOI":"10.1145\/1057661.1057675"},{"key":"470_CR12","unstructured":"Liu, C. H. et al. (2005). Hierarchical instruction encoding for VLIW digital signal processors. In Proc. ISCAS, May 2005, pp.3503\u20133506."},{"key":"470_CR13","unstructured":"Wu, C. et al. (2006). Integrating compiler and system toolkit flow for embedded VLIW DSP processors. In Proc. RTCSA, Aug. 2006, pp.215\u2013222."},{"key":"470_CR14","unstructured":"Lin, Y. C. et al. (2005). Compiler supports and optimizations for PAC VLIW DSP processors. In Proc. LCPC, Oct. 2005, pp.466\u2013474."},{"key":"470_CR15","doi-asserted-by":"crossref","unstructured":"Chen, C. K. et al. (2007). Enabling compiler flow for embedded VLIW DSP processors with distributed register files. In Proc. LCTES, pp.146\u2013148.","DOI":"10.1145\/1254766.1254793"},{"key":"470_CR16","unstructured":"http:\/\/ipf-orc.sourceforge.net\/"},{"key":"470_CR17","doi-asserted-by":"crossref","unstructured":"Wu, C. J., Chen, S. Y., & Lee, J. K. (2007). Copy propagation optimizations for VLIW DSP processors with distributed register files. Languages and Compilers for Parallel Computing (LNCS 4382), pp.251\u2013266, Jun. 2007.","DOI":"10.1007\/978-3-540-72521-3_19"},{"key":"470_CR18","doi-asserted-by":"crossref","first-page":"269","DOI":"10.1007\/s11265-007-0059-4","volume":"51","author":"YC Lin","year":"2008","unstructured":"Lin, Y. C., et al. (2008). Effective code generation for distributed and ping-pong register files: a case study on PAC VLIW DSP cores. Journal of Signal Processing Systems, 51, 269\u2013288.","journal-title":"Journal of Signal Processing Systems"},{"key":"470_CR19","doi-asserted-by":"crossref","first-page":"2391","DOI":"10.1002\/cpe.1176","volume":"19","author":"YJ Lin","year":"2007","unstructured":"Lin, Y. J., You, Y. P., & Lee, J. K. (2007). PALF: compiler supports for irregular register files in clustered VLIW DSP processors. Concurrency and Computation: Practice and Experience, 19, 2391\u20132406.","journal-title":"Concurrency and Computation: Practice and Experience"},{"key":"470_CR20","doi-asserted-by":"crossref","first-page":"101","DOI":"10.1002\/cpe.1334","volume":"21","author":"CH Lu","year":"2009","unstructured":"Lu, C. H., Lin, Y. J., You, Y. P., & Lee, J. K. (2009). LC-GRFA: global register file assignment with local consciousness for VLIW DSP processors with non-uniform register files. Concurrency and Computation: Practice and Experience, 21, 101\u2013114.","journal-title":"Concurrency and Computation: Practice and Experience"},{"key":"470_CR21","unstructured":"Zivojnovic, V., Martinez, J., Schl\u00e4ger, C., & Meyr, H. (1994). DSPstone: a DSP-oriented benchmarking methodology. In Proc. ICSPAT, Oct. 1994."},{"key":"470_CR22","unstructured":"http:\/\/www.gnu.org\/software\/gdb\/"},{"key":"470_CR23","unstructured":"Eclipse Platform Technical Overview, available online: http:\/\/www.eclipse.org\/articles\/Whitepaper-Platform-3.1\/eclipse-platform-whitepaper.pdf"},{"key":"470_CR24","doi-asserted-by":"crossref","first-page":"257","DOI":"10.1007\/s11265-007-0060-y","volume":"51","author":"KY Hsieh","year":"2008","unstructured":"Hsieh, K. Y., Lin, Y. C., Huang, C. C., & Lee, J. K. (2008). Enhancing microkernel performance on VLIW DSP processors via multiset context switch. Journal of Signal Processing Systems, 51, 257\u2013268.","journal-title":"Journal of Signal Processing Systems"},{"key":"470_CR25","first-page":"84","volume":"3","author":"CY Lai","year":"2005","unstructured":"Lai, C. Y., Lin, J. H., & Wang, Y. F. (2005). DVFS SoC architecture and implementation. SoC Technology Journal, 3, 84\u201391.","journal-title":"SoC Technology Journal"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0470-0.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-010-0470-0\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0470-0","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T12:19:33Z","timestamp":1559391573000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-010-0470-0"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,4,20]]},"references-count":25,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2011,3]]}},"alternative-id":["470"],"URL":"https:\/\/doi.org\/10.1007\/s11265-010-0470-0","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,4,20]]}}}