{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,4,5]],"date-time":"2022-04-05T06:25:23Z","timestamp":1649139923622},"reference-count":33,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2010,12,1]],"date-time":"2010-12-01T00:00:00Z","timestamp":1291161600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2012,4]]},"DOI":"10.1007\/s11265-010-0559-5","type":"journal-article","created":{"date-parts":[[2010,11,30]],"date-time":"2010-11-30T06:33:21Z","timestamp":1291098801000},"page":"3-13","source":"Crossref","is-referenced-by-count":0,"title":["Reconfigurable Blocks Based on Balanced Ternary"],"prefix":"10.1007","volume":"67","author":[{"given":"Paul","family":"Beckett","sequence":"first","affiliation":[]},{"given":"Tayab","family":"Memon","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2010,12,1]]},"reference":[{"key":"559_CR1","unstructured":"Knuth, D. E. (1981). The art of computer programming, (Vol. 2). Reading, Mass.: Addison-Wesley Publishing Company."},{"issue":"6","key":"559_CR2","doi-asserted-by":"crossref","first-page":"1605","DOI":"10.1109\/78.139273","volume":"40","author":"P Wong","year":"1992","unstructured":"Wong, P. (1992). Fully sigma-delta modulation encoded FIR filters. IEEE Transactions on Signal Processing, 40(6), 1605\u20131610.","journal-title":"IEEE Transactions on Signal Processing"},{"issue":"2","key":"559_CR3","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1049\/ep.1964.0037","volume":"10","author":"W Alexander","year":"1964","unstructured":"Alexander, W. (1964). The ternary computer. Electronics and Power, 10(2), 36\u201339.","journal-title":"Electronics and Power"},{"key":"559_CR4","doi-asserted-by":"crossref","unstructured":"Beckett, P. (2009). Towards a balanced ternary FPGA. In International conference on field-programmable technology, FPT 2009 (pp. 46\u201353).","DOI":"10.1109\/FPT.2009.5377659"},{"key":"559_CR5","unstructured":"DeHon, A. (1996). Reconfigurable architectures for general-purpose computing. MIT A.I. Technical Report 1586."},{"key":"559_CR6","unstructured":"Sapphicon Semiconductor (2010). Available: http:\/\/www.sapphicon.com\/ ."},{"key":"559_CR7","unstructured":"SIA (2009). International technology roadmap for semiconductors, process integraton devices and structures, 2009. Semiconductor industry association. Available: http:\/\/www.itrs.net\/Links\/2009ITRS\/2009Chapters_2009Tables\/2009_PIDS.pdf ."},{"key":"559_CR8","unstructured":"The Mosis Service (1981). Available: http:\/\/www.mosis.com\/"},{"issue":"2","key":"559_CR9","doi-asserted-by":"crossref","first-page":"164","DOI":"10.1109\/LSP.2003.821734","volume":"11","author":"A Thompson","year":"2004","unstructured":"Thompson, A., O\u2019Shea, P., Hussain, Z., & Steele, B. (2004). Efficient single-bit ternary digital filtering using sigma-delta modulator. IEEE Signal Processing Letters, 11(2), 164\u2013166.","journal-title":"IEEE Signal Processing Letters"},{"issue":"1","key":"559_CR10","doi-asserted-by":"crossref","first-page":"31","DOI":"10.1080\/1448837X.2005.11464112","volume":"2","author":"AC Thompson","year":"2005","unstructured":"Thompson, A. C., Hussain, Z. M. & O\u2019Shea, P. (2005). A single-bit narrow-band bandpass digital filter. Australian Journal of Electrical and Electronics Engineering, 2(1), 31\u201340.","journal-title":"Australian Journal of Electrical and Electronics Engineering"},{"issue":"7","key":"559_CR11","doi-asserted-by":"crossref","first-page":"420","DOI":"10.1049\/el:20064257","volume":"42","author":"Z Sadik","year":"2006","unstructured":"Sadik, Z., Hussain, Z. M., & O\u2019Shea, P. (2006). An adaptive algorithm for ternary filtering. IEE Electronics Letters, 42(7), 420\u2013421.","journal-title":"IEE Electronics Letters"},{"key":"559_CR12","doi-asserted-by":"crossref","unstructured":"Rajashekhara T., & Chen, I.-S. (1990). A fast adder design using signed-digit numbers and ternary logic. In Proceedings of the 1990 IEEE Southern Tier technical conference (pp. 187\u2013194).","DOI":"10.1109\/STIER.1990.324644"},{"issue":"1","key":"559_CR13","doi-asserted-by":"crossref","first-page":"75","DOI":"10.1155\/1996\/94696","volume":"4","author":"A Srivastava","year":"1996","unstructured":"Srivastava A., & Venkatapathy, K. (1996). Design and implementation of a low power ternary full adder. VLSI Design, 4(1), 75\u201381.","journal-title":"VLSI Design"},{"issue":"6","key":"559_CR14","doi-asserted-by":"crossref","first-page":"1444","DOI":"10.1109\/16.137325","volume":"39","author":"T Shibata","year":"1992","unstructured":"Shibata T., & Ohmi, T. (1992). A functional MOS transistor featuring gate-level weighted sum and threshold operations. IEEE Transactions on Electron Devices, 39(6), 1444\u20131455.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"559_CR15","unstructured":"Gundersen H., & Berg, Y. (2006). A novel balanced ternary adder using recharged semi-floating gate devices. In ISMVL \u201906: Proceedings of the 36th international symposium on multiple-valued logic (p. 18). Washington: IEEE Computer Society."},{"issue":"6","key":"559_CR16","doi-asserted-by":"crossref","first-page":"1114","DOI":"10.1109\/TVLSI.2003.819571","volume":"11","author":"T Felicijan","year":"2003","unstructured":"Felicijan T., & Furber, S. (2003). An asynchronous ternary logic signaling system. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 11(6), 1114\u20131119.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"559_CR17","doi-asserted-by":"crossref","unstructured":"Philippe, J.-M., Kinvi-Boh, E., Pillement, S., & Sentieys, O. (2006). An energy-efficient ternary interconnection link for asynchronous systems. In Proceedings of the IEEE international symposium on circuits and systems, ISCAS 2006 (pp. 1011\u20131014).","DOI":"10.1109\/ISCAS.2006.1692759"},{"key":"559_CR18","doi-asserted-by":"crossref","first-page":"515","DOI":"10.1145\/1403375.1403499","volume-title":"DATE \u201908: Proceedings of the conference on design, automation and test in Europe","author":"C Duan","year":"2008","unstructured":"Duan C., & Khatri, S. P. (2008). Energy efficient and high speed on-chip ternary bus. In DATE \u201908: Proceedings of the conference on design, automation and test in Europe (pp. 515\u2013518). New York: ACM."},{"key":"559_CR19","volume-title":"Lecture Notes in computer science: Knowledge-based intelligent information and engineering systems(Vol. 5179)","author":"E Sipos","year":"2008","unstructured":"Sipos, E., Festila, L., & Oltean, G. (2008). Towards reconfigurable circuits based on ternary controlled analog multiplexers\/demultiplexers. In I. Lovrek, R. Howlett, & L. Jain (Eds.), Lecture Notes in computer science: Knowledge-based intelligent information and engineering systems (Vol. 5179). Berlin\/Heidelberg: Springer-Verlag."},{"key":"559_CR20","unstructured":"Kang, S.-M., & Leblebici, Y. (1996). CMOS digital integrated circuits: Analysis and design. McGraw-Hill."},{"issue":"2","key":"559_CR21","first-page":"93","volume":"12","author":"K Kuhn","year":"2008","unstructured":"Kuhn, K., Kenyon, C., Kornfeld, A., Liu, M., Maheshwari, A., kai Shih, W., et al. (2008). Managing process variation in Intel\u2019s 45 nm CMOS technology. Intel Technology Journal, 12(2), 93\u2013109.","journal-title":"Intel Technology Journal"},{"key":"559_CR22","doi-asserted-by":"crossref","unstructured":"Calhoun, B., Khanna, S., Mann, R., & Wang, J. (2009). Sub-threshold circuit design with shrinking cmos devices. In IEEE international symposium on circuits and systems, ISCAS 2009 (pp. 2541\u20132544).","DOI":"10.1109\/ISCAS.2009.5118319"},{"key":"559_CR23","unstructured":"Tsunomura, T., Nishida, A., Yano, F., Putra, A., Takeuchi, K., Inaba, S., et al. (2009). Analysis of extra vt variability sources in nmos using takeuchi plot. In IEEE symposium on VLSI technology (pp. 110\u2013111)."},{"key":"559_CR24","unstructured":"Andrieu, F., Weber, O., Mazurier, J., & Faynot, O. (2010). Planar fully depleted SOI: Technological solution against variability, solid state technology. Available: http:\/\/online.qmags.com\/SST1110 ."},{"key":"559_CR25","doi-asserted-by":"crossref","unstructured":"Cheng, K., Khakifirooz, A., Kulkarni, P., Ponoth, S., Kuss, J., Shahrjerdi, D., et al. (2009). Extremely thin SOI (ETSOI) CMOS with record low variability for low power system-on-chip applications. In IEEE international electron devices meeting (IEDM 2009) (pp. 1\u20134).","DOI":"10.1109\/IEDM.2009.5424422"},{"key":"559_CR26","doi-asserted-by":"crossref","unstructured":"Connell, C., & Balsara, P. (2001). A novel single-rail variable encoded completion detection scheme for self-timed circuit design using ternary multiple valued logic. In Proceedings of the IEEE 2nd Dallas CAS workshop on low power\/low voltage mixed-signal circuits and systems, 2001. (DCAS-01) (pp. P7\u201310).","DOI":"10.1109\/DCAS.2001.920983"},{"issue":"1","key":"559_CR27","doi-asserted-by":"crossref","first-page":"10","DOI":"10.1109\/54.655177","volume":"15","author":"V Betz","year":"1998","unstructured":"Betz, V., & Rose, J. (1998). How much logic should go in an FPGA logic block? IEEE Design and Test of Computers, 15(1), 10\u201315.","journal-title":"IEEE Design and Test of Computers"},{"issue":"3","key":"559_CR28","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2004.824300","volume":"12","author":"E Ahmed","year":"2004","unstructured":"Ahmed, E., & Rose, J. (2004). The effect of LUT and cluster size on deep-submicron FPGA performance and density. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 12(3), 288\u2013298.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"issue":"6","key":"559_CR29","doi-asserted-by":"crossref","first-page":"1082","DOI":"10.1109\/JSSC.1986.1052651","volume":"sc-21","author":"KM Chu","year":"1986","unstructured":"Chu, K. M., & Pulfrey, D. (1986). Design procedures for differential cascode voltage switch circuits. IEEE Journal of Solid-State Circuits, sc-21(6), 1082\u20131087.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"559_CR30","doi-asserted-by":"crossref","unstructured":"Fan, H., Liu, J., Wu, Y.-L., & Cheung, C.-C. (2001). On optimum switch box designs for 2-D FPGAs. In Proceedings of the design automation conference, DAC 2001 (pp. 203\u2013208).","DOI":"10.1145\/378239.378464"},{"key":"559_CR31","doi-asserted-by":"crossref","unstructured":"Fan, H., & Wu, Y.-L. (2005). Crossbar based design schemes for switch boxes and programmable interconnection networks. In Proceedings of the Asia and South Pacific design automation conference, ASP-DAC 2005 (Vol. 2, pp. 910\u2013915).","DOI":"10.1145\/1120725.1121068"},{"key":"559_CR32","doi-asserted-by":"crossref","unstructured":"Brayton, R., & Khatri, S. (1999). Multi-valued logic synthesis. In Proceedings of the twelfth international conference on VLSI design (pp. 196\u2013205).","DOI":"10.1109\/ICVD.1999.745148"},{"key":"559_CR33","unstructured":"Memon, T. D., Beckett, P., & Hussain, Z. M. (2009). Design and implementation of ternary fir filter using sigma delta modulation. In Proceedings of the international symposium on computing, communication, and control (ISCCC\u201909)."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0559-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-010-0559-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0559-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,6]],"date-time":"2019-06-06T13:32:49Z","timestamp":1559827969000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-010-0559-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2010,12,1]]},"references-count":33,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,4]]}},"alternative-id":["559"],"URL":"https:\/\/doi.org\/10.1007\/s11265-010-0559-5","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2010,12,1]]}}}