{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,12,29]],"date-time":"2022-12-29T18:28:20Z","timestamp":1672338500297},"reference-count":29,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2011,1,5]],"date-time":"2011-01-05T00:00:00Z","timestamp":1294185600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1007\/s11265-010-0575-5","type":"journal-article","created":{"date-parts":[[2011,1,4]],"date-time":"2011-01-04T02:32:29Z","timestamp":1294108349000},"page":"49-62","source":"Crossref","is-referenced-by-count":4,"title":["Bit-by-Bit Pipelined and Hybrid-Grained 2D Architecture for Motion Estimation of H.264\/AVC"],"prefix":"10.1007","volume":"68","author":[{"given":"Yang","family":"Song","sequence":"first","affiliation":[]},{"given":"Ali","family":"Akoglu","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2011,1,5]]},"reference":[{"issue":"7","key":"575_CR1","doi-asserted-by":"crossref","first-page":"560","DOI":"10.1109\/TCSVT.2003.815165","volume":"13","author":"T Wiegand","year":"2003","unstructured":"Wiegand, T., Sullivan, G. J., Bjontegaard, G., & Luthra, A. (2003). Overview of the H.264\/AVC video coding standard. IEEE Transactions on Circuits and Systems for Video Technology, 13(7), 560\u2013576.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"575_CR2","doi-asserted-by":"crossref","first-page":"42","DOI":"10.1109\/76.825857","volume":"10","author":"I Rhee","year":"2000","unstructured":"Rhee, I., et. al. (2000). Quadtree-structured variable-size block-matching motion estimation with minimal error. IEEE Transactions on Circuits and Systems for Video Technology, 10, 42\u201350.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"1","key":"575_CR3","first-page":"77","volume":"51","author":"BMH Li","year":"2008","unstructured":"Li, B. M. H., & Leong, P. H. W. (2008). Serial and parallel FPGA-based variable block size motion estimation processors. Journal of VLSI Signal Processing, 51(1), 77\u201398.","journal-title":"Journal of VLSI Signal Processing"},{"key":"575_CR4","unstructured":"Su, C.-L., & Jen, C.-W. (2000). Motion estimation using on-line arithmetic. In IEEE international symposium on circuits and systems (Vol. 1)."},{"issue":"5","key":"575_CR5","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1016\/j.micpro.2005.12.006","volume":"30","author":"J Olivares","year":"2006","unstructured":"Olivares, J., Hormigo, J., Villalba, J., Benavides, I., & Zapata, E. L. (2006). SAD computation based on online arithmetic for motion estimation. Microprocessors and Microsystems, 30(5), 250\u2013258.","journal-title":"Microprocessors and Microsystems"},{"key":"575_CR6","doi-asserted-by":"crossref","unstructured":"Marshall, A., et al. (1999). A reconfigurable arithmetic array for multimedia applications. In Proc. ACM\/SIGDA FPGA\u201999, Monterey, 21\u201323 Feb. 1999.","DOI":"10.1145\/296399.296444"},{"key":"575_CR7","unstructured":"Ebeling, C., Cronquist, D. C., Franklin, P., & Fisher, C. (1996). RaPiD\u2014a configurable computing architecture for compute-intensive applications. University of Washington Department of Computer Science & Engineering Tech Report, TR-96-11-03."},{"key":"575_CR8","doi-asserted-by":"crossref","unstructured":"Verma, R., & Akoglu, A. (2007). A coarse grained reconfigurable architecture for variable size block motion estimation. In IEEE international conference on field-programmable technology 2007 (ICFPT\u201907) (pp. 81\u201388). Kitakyushu, Japan.","DOI":"10.1109\/FPT.2007.4439235"},{"issue":"2","key":"575_CR9","doi-asserted-by":"crossref","first-page":"578","DOI":"10.1109\/TCSI.2005.858488","volume":"53","author":"CY Chen","year":"2006","unstructured":"Chen, C. Y., Chien, S. Y., Huang, Y. W., Chen, T. C., Wang, T. C., & Chen, L. G. (2006). Analysis and architecture design of variable block-size motion estimation for H.264\/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 53(2), 578\u2013593.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"5","key":"575_CR10","doi-asserted-by":"crossref","first-page":"568","DOI":"10.1109\/TCSVT.2007.894044","volume":"17","author":"TC Chen","year":"2007","unstructured":"Chen, T. C., Chen, Y. H., Tsai, S. F., Chien, S. Y., & Chen, L. G. (2007). Fast algorithm and architecture design of low-power integer motion estimation for H.264\/AVC. IEEE Transactions on Circuits and Systems for Video Technology, 17(5), 568\u2013577.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"6","key":"575_CR11","doi-asserted-by":"crossref","first-page":"673","DOI":"10.1109\/TCSVT.2006.873163","volume":"16","author":"TC Chen","year":"2006","unstructured":"Chen, T. C., Chien, S. Y., Huang, Y. W., Tsai, C. H., Chen, C. Y., Chen, T. W., et al. (2006). Analysis and architecture design of an HDTV720p 30frames\/s H.264\/AVC encoder. IEEE Transactions on Circuits and Systems for Video Technology, 16(6), 673\u2013688.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"3","key":"575_CR12","first-page":"22","volume":"22","author":"TC Chen","year":"2006","unstructured":"Chen, T. C., Fang, H. C., Lian, C. J. Tsai, C. H., Huang, Y. W., Chen, T. W., et al. (2006). Algorithm analysis and architecture design for HDTV applications\u2014a look at the H.264\/AVC video compressor system. IEEE Transactions on Circuits and Systems for Video Technology, 22(3), 22\u201331.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"575_CR13","doi-asserted-by":"crossref","unstructured":"Kim, M., Hwang, I., & Chae, S. I. (2005). A fast VLSI architecture for full-search variable block size motion estimation in MPEG-4 AVC\/H.264. In Proc. ASP-DAC (Vol. 1, pp. 631\u2013634).","DOI":"10.1145\/1120725.1120980"},{"key":"575_CR14","unstructured":"Lappalainen, V., Hailapuro, A., Hamalainen, T. D., & Nokia Res. Center, Tampere (2002). Performance of H.26L video encoder on general-purpose processor. The Journal of VLSI Signal Processing."},{"key":"575_CR15","doi-asserted-by":"crossref","unstructured":"Reader, S., & Meng, T. (1999). Performance evaluation of motion estimation algorithms for digital signal processors. Tech. Report, Stanford University.","DOI":"10.1109\/SIPS.1999.822308"},{"key":"575_CR16","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1023\/A:1008192719838","volume":"23","author":"PM Kuhn","year":"1999","unstructured":"Kuhn, P. M. (1999). Fast MPEG-4 motion estimation: Processor based and flexible VLSI implementations. Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 23, 67\u201392.","journal-title":"Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology"},{"issue":"7","key":"575_CR17","doi-asserted-by":"crossref","first-page":"890","DOI":"10.1109\/76.931116","volume":"11","author":"JF Shen","year":"2001","unstructured":"Shen, J. F., et al. (2001). A Novel low-power full-search block-matching motion-estimation design for H.263+. IEEE Transactions on Circuits and Systems for Video Technology, 11(7), 890\u2013897.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"575_CR18","doi-asserted-by":"crossref","first-page":"417","DOI":"10.1109\/76.473554","volume":"5","author":"L Vos de","year":"1995","unstructured":"de Vos, L., & Schobinger, M. (1995). VLSI architecture for a flexible block matching processor. IEEE Transactions Circuits and Systems for Video Technology, 5, 417\u2013428.","journal-title":"IEEE Transactions Circuits and Systems for Video Technology"},{"issue":"7","key":"575_CR19","doi-asserted-by":"crossref","first-page":"384","DOI":"10.1109\/TCSII.2004.829555","volume":"51","author":"SY Yap","year":"2004","unstructured":"Yap, S. Y., & McCanny, J. V. (2004). A VLSI architecture for variable block size video motion estimation. IEEE Transactions on CAS II, 51(7), 384\u2013389.","journal-title":"IEEE Transactions on CAS II"},{"issue":"4","key":"575_CR20","doi-asserted-by":"crossref","first-page":"1291","DOI":"10.1109\/TCE.2005.1561858","volume":"51","author":"C-M Ou","year":"2005","unstructured":"Ou, C.-M., Le, C.-F., & Hwang, W.-J. (2005). An efficient VLSI architecture for H.264 variable block size motion estimation. IEEE Transaction on Consumer Electronics, 51(4), 1291\u20131299.","journal-title":"IEEE Transaction on Consumer Electronics"},{"key":"575_CR21","doi-asserted-by":"crossref","unstructured":"Yap, S. Y., & McCanny, J. V. (2003). A VLSI architecture for advanced video coding motion estimation. In Proc. IEEE intl. conf. applications-specific systems, arch., processors (pp. 293\u2013301).","DOI":"10.1109\/ASAP.2003.1212853"},{"key":"575_CR22","unstructured":"Soohoo, A. (2005). FPGA co-processing architectures for video compression. Altera Corporation."},{"issue":"9","key":"575_CR23","doi-asserted-by":"crossref","first-page":"86","DOI":"10.1109\/2.612254","volume":"30","author":"E Waingold","year":"1997","unstructured":"Waingold, E., et al. (1997). Baring it all to software: RAW machines. IEEE Computer, 30(9), 86\u201393.","journal-title":"IEEE Computer"},{"key":"575_CR24","doi-asserted-by":"crossref","unstructured":"Mirsky, E., & DeHon, A. (1996). MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources. In Proc. IEEE FCCM\u201996, Napa, CA, USA, 17\u201319 April 1996.","DOI":"10.1109\/FPGA.1996.564808"},{"issue":"10","key":"575_CR25","doi-asserted-by":"crossref","first-page":"1317","DOI":"10.1109\/31.44348","volume":"36","author":"KM Yang","year":"1989","unstructured":"Yang, K. M., Sun, M. T., & Wu, L. (1989). A family of VLSI designs for the motion compensation block-matching algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 36(10), 1317\u20131325.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"2","key":"575_CR26","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1109\/76.664095","volume":"8","author":"YK Lai","year":"1998","unstructured":"Lai, Y. K., & Chen, L. G. (1998). A data-interlacing architecture with two dimensional data-reuse for full-search block-matching algorithm. IEEE Transactions on Circuits and Systems for Video Technology, 8(2), 124\u2013127.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"issue":"5","key":"575_CR27","doi-asserted-by":"crossref","first-page":"407","DOI":"10.1109\/76.473553","volume":"5","author":"H Yeo","year":"1995","unstructured":"Yeo, H., & Hu, Y. H. (1995). A novel modular systolic array architecture for full-search block matching motion estimation. IEEE Transactions on Circuits and Systems for Video Technology, 5(5), 407\u2013416.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"575_CR28","unstructured":"Ercegovac, M. D., & Lang, T. (1989). On-line arithmetic for DSP applications. In 32nd Midwest symposium on circuits and systems, Urbana."},{"issue":"9","key":"575_CR29","doi-asserted-by":"crossref","first-page":"389","DOI":"10.1109\/TEC.1961.5219227","volume":"EC-10","author":"A Avizienis","year":"1961","unstructured":"Avizienis, A. (1961). Signed-digit number representations for fast parallel arithmetic. IRE Transactions on Electronic Computers, EC-10(9), 389\u2013400.","journal-title":"IRE Transactions on Electronic Computers"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0575-5.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-010-0575-5\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-010-0575-5","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,7]],"date-time":"2019-06-07T10:47:26Z","timestamp":1559904446000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-010-0575-5"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,1,5]]},"references-count":29,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,7]]}},"alternative-id":["575"],"URL":"https:\/\/doi.org\/10.1007\/s11265-010-0575-5","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,1,5]]}}}