{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2022,3,31]],"date-time":"2022-03-31T16:46:53Z","timestamp":1648745213132},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2011,5,13]],"date-time":"2011-05-13T00:00:00Z","timestamp":1305244800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2012,7]]},"DOI":"10.1007\/s11265-011-0589-7","type":"journal-article","created":{"date-parts":[[2011,5,12]],"date-time":"2011-05-12T10:08:38Z","timestamp":1305194918000},"page":"127-138","source":"Crossref","is-referenced-by-count":1,"title":["A Low Cost Architecture for Variable Block Size Motion Estimation"],"prefix":"10.1007","volume":"68","author":[{"given":"Joaqu\u00edn","family":"Olivares","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2011,5,13]]},"reference":[{"key":"589_CR1","unstructured":"Mohammadzadeh, M., Eshghi, M., & Azadfar, M.\u00a0M. (2004). Parameterizable implementation of full search block matching algorithm using FPGA for real-time applications. In ICCDCS 2004: Fifth international Caracas conference on devices, circuits and systems (pp. 200\u2013203)."},{"key":"589_CR2","doi-asserted-by":"crossref","unstructured":"Huang, Y., Chien, S., Hsieh, B., & Chen, L. (2004). Global elimination algorithm and architecture design for fast block matching motion estimation. IEEE Transactions On Circuits And Systems For Video Technology, 14(6), 898\u2013907.","DOI":"10.1109\/TCSVT.2004.828321"},{"issue":"2","key":"589_CR3","doi-asserted-by":"crossref","first-page":"101","DOI":"10.1109\/6046.845014","volume":"2","author":"T Shanableh","year":"2000","unstructured":"Shanableh, T., & Ghanbari, M. (2000). Heterogeneous video transcoding to lower spatio-temporal resolutions and different encoding formats. IEEE Transactions on Multimedia, 2(2), 101\u2013110.","journal-title":"IEEE Transactions on Multimedia"},{"key":"589_CR4","doi-asserted-by":"crossref","DOI":"10.1007\/978-1-4615-6199-6","volume-title":"Image and video compression standards: Algorithms and architectures","author":"V Bhaskaran","year":"1997","unstructured":"Bhaskaran, V., & Konstantinides, K. (1997). Image and video compression standards: Algorithms and architectures (2nd ed.). Norwell: Kluwer.","edition":"2"},{"key":"589_CR5","doi-asserted-by":"crossref","first-page":"2355","DOI":"10.1109\/TSP.2002.801888","volume":"50","author":"J Kim","year":"2002","unstructured":"Kim, J., Byun, S., Kim, Y., & Ahn, B. (2002). Fast full search motion estimation algorithm using early detection of impossible candidate vectors. IEEE Transactions on Signal Processing, 50, 2355\u20132365.","journal-title":"IEEE Transactions on Signal Processing"},{"key":"589_CR6","doi-asserted-by":"crossref","first-page":"1223","DOI":"10.1109\/83.935038","volume":"10","author":"Y Chan","year":"2001","unstructured":"Chan, Y., & Siu, W. (2001). An efficient search strategy for block motion estimation using image features. IEEE Transactions on Image Processing, 10, 1223\u20131238.","journal-title":"IEEE Transactions on Image Processing"},{"key":"589_CR7","doi-asserted-by":"crossref","unstructured":"Ghanbari, M. (2003). Standard codecs: Image compression to advanced video coding. The Institution of Electrical Engineer.","DOI":"10.1049\/PBTE049E"},{"key":"589_CR8","doi-asserted-by":"crossref","unstructured":"Wong, S., Vassiliadis, S., & Cotofana, S. (2002). A sum of absolute differences implementation in FPGA hardware. In 28th Euromicro conference (EUROMICRO\u201902) (pp. 183\u2013188). Dortmund, Germany.","DOI":"10.1109\/EURMIC.2002.1046155"},{"key":"589_CR9","doi-asserted-by":"crossref","first-page":"67","DOI":"10.1109\/76.486421","volume":"6","author":"SB Pan","year":"1996","unstructured":"Pan, S. B., Chae, S. S., & Park, R. H. (1996). VLSI architecture for block matching algorithms using systolic arrays. IEEE Transactions on Circuits and Systems for Video Technology, 6, 67\u201373.","journal-title":"IEEE Transactions on Circuits and Systems for Video Technology"},{"key":"589_CR10","doi-asserted-by":"crossref","first-page":"389","DOI":"10.1109\/TEC.1961.5219227","volume":"EC-10","author":"A Avizienis","year":"1961","unstructured":"Avizienis, A. (1961). Signed digit number representation for fast parallel arithmetic. IRE Transactions on Electronic Computers, EC-10, 389\u2013400.","journal-title":"IRE Transactions on Electronic Computers"},{"key":"589_CR11","unstructured":"Ercegovac, M., & Lang, T. (1989). On-line arithmetic for DSP applications. In 32nd Midwest symposium on circuits and systems (pp. 365\u2013368)."},{"key":"589_CR12","volume-title":"Digital arithmetic","author":"M Ercegovac","year":"2004","unstructured":"Ercegovac, M., & Lang, T. (2004). Digital arithmetic. San Mateo: Morgan Kaufmann."},{"key":"589_CR13","unstructured":"Muller. J.\u00a0M. (1991). On-line computations: A survey and some new results. In IFIP workshop on algorithms and parallel VLSI architectures. Bonas, France."},{"issue":"2","key":"589_CR14","doi-asserted-by":"crossref","first-page":"124","DOI":"10.1049\/ip-cds:20030332","volume":"150","author":"C Su","year":"2003","unstructured":"Su, C., & Jen, C. (2003). Motion estimation using MSD-first processing. IEE Proceedings. Circuits, Devices and Systems, 150(2), 124\u2013133.","journal-title":"IEE Proceedings. Circuits, Devices and Systems"},{"issue":"5","key":"589_CR15","doi-asserted-by":"crossref","first-page":"250","DOI":"10.1016\/j.micpro.2005.12.006","volume":"30","author":"J Olivares","year":"2006","unstructured":"Olivares, J., Hormigo, J., Villalba, J., Benavides, J. I., & Zapata, E. (2006). SAD computation based on online arithmetic for motion estimation. Microprocessors and Microsystems, 30(5), 250\u2013258.","journal-title":"Microprocessors and Microsystems"},{"issue":"1","key":"589_CR16","doi-asserted-by":"crossref","first-page":"77","DOI":"10.1007\/s11265-007-0143-9","volume":"51","author":"BMH Li","year":"2008","unstructured":"Li, B. M. H., & Leong, P. H. W. (2008). Serial and parallel FPGA-based variable block size motion estimation processors. Journal of Signal Processing Systems, 51(1), 77\u201398.","journal-title":"Journal of Signal Processing Systems"},{"issue":"3","key":"589_CR17","doi-asserted-by":"crossref","first-page":"1338","DOI":"10.1109\/TCE.2008.4637625","volume":"54","author":"C Wei","year":"2008","unstructured":"Wei, C., Hui, H., Jiarong, T., Jinmei, L., & Hao, M. (2008). A high-performance reconfigurable VLSI architecture for VBSME in H.264. IEEE Transactions on Consumer Electronics, 54(3), 1338\u20131345.","journal-title":"IEEE Transactions on Consumer Electronics"},{"issue":"2","key":"589_CR18","doi-asserted-by":"crossref","first-page":"578","DOI":"10.1109\/TCSI.2005.858488","volume":"53","author":"C-Y Chen","year":"2006","unstructured":"Chen, C.-Y., Chien, S.-Y., Huang, Y.-W., Chen, T.-C., Wang, T.-C., & Chen, L.-G. (2006). Analysis and architecture design of variable block-size motion estimation for H.264\/AVC. IEEE Transactions on Circuits and Systems-I: Regular Papers, 53(2), 578\u2013593.","journal-title":"IEEE Transactions on Circuits and Systems-I: Regular Papers"},{"issue":"9","key":"589_CR19","doi-asserted-by":"crossref","first-page":"912","DOI":"10.1109\/TCSII.2008.923398","volume":"55","author":"M Sayed","year":"2008","unstructured":"Sayed, M., Badawy, W., & Jullien, G. (2008). Towards an H.264\/AVC HW\/SW integrated solution: An efficient VBSME architecture. IEEE Transactions on Circuits and Systems-II: Express Briefs, 55(9), 912\u2013916.","journal-title":"IEEE Transactions on Circuits and Systems-II: Express Briefs"},{"key":"589_CR20","doi-asserted-by":"crossref","unstructured":"Liu, Z., Huang, Y., Song, Y., Goto, S., & Ikenaga, T. (2007). Hardware-efficient propagate partial sad architecture for variable block size motion estimation in H.264\/AVC. In Proceedings of ACM Great Lakes symposium on VLSI\u20192007 (pp. 160\u2013163).","DOI":"10.1145\/1228784.1228826"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0589-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-011-0589-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0589-7","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,10]],"date-time":"2019-06-10T18:49:31Z","timestamp":1560192571000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-011-0589-7"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,5,13]]},"references-count":20,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2012,7]]}},"alternative-id":["589"],"URL":"https:\/\/doi.org\/10.1007\/s11265-011-0589-7","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,5,13]]}}}