{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,13]],"date-time":"2025-05-13T09:26:06Z","timestamp":1747128366103},"reference-count":62,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2011,8,10]],"date-time":"2011-08-10T00:00:00Z","timestamp":1312934400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2012,2]]},"DOI":"10.1007\/s11265-011-0607-9","type":"journal-article","created":{"date-parts":[[2011,8,9]],"date-time":"2011-08-09T18:00:06Z","timestamp":1312912806000},"page":"191-221","source":"Crossref","is-referenced-by-count":6,"title":["Deployment of Run-Time Reconfigurable Hardware Coprocessors Into Compute-Intensive Embedded Applications"],"prefix":"10.1007","volume":"66","author":[{"given":"Francisco","family":"Fons","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mariano","family":"Fons","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Enrique","family":"Cant\u00f3","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Mariano","family":"L\u00f3pez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2011,8,10]]},"reference":[{"issue":"2","key":"607_CR1","doi-asserted-by":"crossref","first-page":"247","DOI":"10.1109\/92.678880","volume":"6","author":"MJ Wirthlin","year":"1998","unstructured":"Wirthlin, M. J., & Hutchings, B. L. (1998). Improving functional density using run-time circuit reconfiguration. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 6(2), 247\u2013256.","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"607_CR2","doi-asserted-by":"crossref","unstructured":"Delahaye, J. -P., Gogniat, G., Roland, C., & Bomel, P. (2004). Software radio and dynamic reconfiguration on a DSP\/FPGA platform. Frequenz, Journal of RF-Engineering and Telecommunications, 58.","DOI":"10.1515\/FREQ.2004.58.5-6.152"},{"key":"607_CR3","unstructured":"Nezami, K. G., Stephens, P. W., & Walker, S. D. (2008). Handel-C implementation of early-access partial-reconfiguration for software defined radio, WCNC 2008 proceedings, IEEE, pp. 1103\u20131108."},{"key":"607_CR4","doi-asserted-by":"crossref","first-page":"73","DOI":"10.1016\/j.phycom.2009.09.002","volume":"3","author":"AR Cormier","year":"2010","unstructured":"Cormier, A. R., Dietrich, C. B., Price, J., & Reed, J. H. (2010). Dynamic reconfiguration of software defined radios using standard architectures. Physical Communication, 3, 73\u201380.","journal-title":"Physical Communication"},{"issue":"1","key":"607_CR5","doi-asserted-by":"crossref","first-page":"3","DOI":"10.1109\/TVLSI.2007.912075","volume":"16","author":"GK Rauwerda","year":"2008","unstructured":"Rauwerda, G. K., Heysters, P. M., & Smit, G. J. M. (2008). Towards software defined radios using coarse-grained reconfigurable hardware. IEEE Transactions of Very Large Scale Integration (VLSI) Systems, 16(1), 3\u201313.","journal-title":"IEEE Transactions of Very Large Scale Integration (VLSI) Systems"},{"key":"607_CR6","doi-asserted-by":"crossref","first-page":"1032","DOI":"10.1016\/j.mejo.2008.11.044","volume":"40","author":"JM Granado","year":"2009","unstructured":"Granado, J. M., Vega-Rodr\u00edguez, M. A., S\u00e1nchez-P\u00e9rez, J. M., & G\u00f3mez-Pulido, J. A. (2009). IDEA and AES, two cryptographic algorithms implemented using partial and dynamic reconfiguration. Microelectronics Journal, 40, 1032\u20131040.","journal-title":"Microelectronics Journal"},{"key":"607_CR7","doi-asserted-by":"crossref","first-page":"72","DOI":"10.1016\/j.vlsi.2009.05.003","volume":"43","author":"JM Granado","year":"2010","unstructured":"Granado, J. M., Vega-Rodr\u00edguez, M. A., S\u00e1nchez-P\u00e9rez, J. M., & G\u00f3mez-Pulido, J. A. (2010). A new methodology to implement the AES algorithm using partial and dynamic reconfiguration. Integration, the VLSI Journal, 43, 72\u201380.","journal-title":"Integration, the VLSI Journal"},{"key":"607_CR8","unstructured":"Gonzalez, I., Lopez-Buedo, S., Gomez, F. J., & Martinez, J. (2003). Using partial reconfiguration in cryptographic applications: an implementation of the IDEA algorithm, FPL 2003, LNCS 2778, pp. 194\u2013203, Springer."},{"key":"607_CR9","doi-asserted-by":"crossref","unstructured":"Hori, Y., Satoh, A., Sakane, H., & Toda, K. (2008). Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 23\u201328.","DOI":"10.1007\/978-3-540-89598-5_18"},{"issue":"5","key":"607_CR10","doi-asserted-by":"crossref","first-page":"1398","DOI":"10.1093\/ietisy\/e91-d.5.1398","volume":"E91-D","author":"Y Hori","year":"2008","unstructured":"Hori, Y., Yokoyamay, H., Sakane, H., & Toda, K. (2008). A secure content delivery system based on a partially reconfigurable FPGA. IEICE Transactions on Information and Systems, E91-D(5), 1398\u20131407.","journal-title":"IEICE Transactions on Information and Systems"},{"key":"607_CR11","doi-asserted-by":"crossref","unstructured":"Osterloh, B., Michalik, H., Fiethe, B., & Bubenhagen, F. (2010). Architecture verification of the SoCWire NoC approach for safe dynamic partial reconfiguration in space applications. NASA\/ESA Conference on Adaptive Hardware and Systems.","DOI":"10.1109\/AHS.2010.5546220"},{"key":"607_CR12","doi-asserted-by":"crossref","unstructured":"Murgan, T., Petrov, M., Majer, M., Zipf, P., Glesner, M., Heinkel, U, et al. (2004). Adaptive architectures for an OTN processor: Reducing design costs through reconfigurability and multiprocessing. Conf. Computing Frontiers, pp. 404\u2013418.","DOI":"10.1145\/977091.977149"},{"key":"607_CR13","doi-asserted-by":"crossref","unstructured":"Guindani, G., Ferlini, F., Oliveira, J., Calazans, N., Pigatto, D., & Moraes, F. (2009). A 10 Gbps OTN framer implementation targeting FPGA devices. Proceedings of the International Conference on Reconfigurable Computing and FPGAs, pp. 30\u201335.","DOI":"10.1109\/ReConFig.2009.27"},{"key":"607_CR14","unstructured":"Fons, F., & Fons, M. (2010). Making biometrics the killer app of FPGA dynamic partial reconfiguration. Xcell Journal, Xilinx, (72), 24\u201331."},{"key":"607_CR15","unstructured":"Sony Corp., CX-NEWS Sony Semiconductor & LCD News (web magazine), vol.42, November 2005, http:\/\/www.sony.net\/Products\/SC-HP\/cx_news\/vol42\/sideview.html ."},{"key":"607_CR16","unstructured":"Lewis, S. (2009). Virtex-5 powers reconfigurable, Rugged PC. Xilinx Xcell Journal, (68), 28\u201331."},{"key":"607_CR17","unstructured":"http:\/\/www.sgi.com\/company_info\/newsroom\/press_releases\/2005\/september\/rasc.html ."},{"key":"607_CR18","unstructured":"Flatley, T. (2010). Advanced hybrid on-board science data processor - SpaceCube 2.0, NASA Earth Science Technology Forum."},{"issue":"3","key":"607_CR19","first-page":"7","volume":"5","author":"TP Flatley","year":"2009","unstructured":"Flatley, T. P. (2009). What would you rather have: more data or perfect data? Goddard Tech Trends, 5(3), 7\u20137.","journal-title":"Goddard Tech Trends"},{"issue":"2","key":"607_CR20","doi-asserted-by":"crossref","first-page":"602","DOI":"10.1109\/TNS.2009.2037916","volume":"57","author":"N Abel","year":"2010","unstructured":"Abel, N., Manz, S., Gr\u00fcll, F., & Kebschull, U. (2010). Increasing design changeability using dynamic partial reconfiguration. IEEE Transactions on Nuclear Science, 57(2), 602\u2013209.","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"607_CR21","doi-asserted-by":"crossref","unstructured":"Jara-Berrocal, A., & Gordon-Ross, A. (2010). VAPRES: A virtual architecture for partially reconfigurable embedded systems. Proceedings of Design, Automation, and Test in Europe Conference.","DOI":"10.1109\/DATE.2010.5456934"},{"key":"607_CR22","doi-asserted-by":"crossref","unstructured":"Garcia, R., Gordon-Ross, A., & George, A. (2009). Exploiting partially reconfigurable FPGAs for situation-based reconfiguration in wireless sensor networks. Proceedings of IEEE Symposium on Field-Programmable Custom Computing Machines.","DOI":"10.1109\/FCCM.2009.45"},{"key":"607_CR23","doi-asserted-by":"crossref","unstructured":"Jara-Berrocal, A., & Gordon-Ross, A. (2009). SCORES: A scalable and parametric streams-based communication architecture for modular reconfigurable systems. Proceedings of Design, Automation, and Test in Europe Conference.","DOI":"10.1109\/DATE.2009.5090669"},{"key":"607_CR24","doi-asserted-by":"crossref","unstructured":"Jara-Berrocal, A., & Gordon-Ross, A. (2009). Runtime temporal partitioning assembly to reduce FPGA reconfiguration time. Proceedings of International Conference on Reconfigurable Computing and FPGAs.","DOI":"10.1109\/ReConFig.2009.61"},{"key":"607_CR25","doi-asserted-by":"crossref","unstructured":"Huebner, M., Ullmann, M., Braun, L., Klausmann, A., Becker, J. (2004). Scalable application-dependent network on chip adaptivity for dynamical reconfigurable real-time systems. Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), LNCS 3203, pp. 1037\u20131041.","DOI":"10.1007\/978-3-540-30117-2_122"},{"key":"607_CR26","doi-asserted-by":"crossref","unstructured":"Ullmann, M., H\u00fcbner, M., Grimm, B., & Becker, J. (2004). On-demand FPGA run-time system for dynamical reconfiguration with adaptive priorities. Proceedings of the International Conference on Field Programmable Logic and Applications, LNCS 3203, pp. 454\u2013463.","DOI":"10.1007\/978-3-540-30117-2_47"},{"key":"607_CR27","unstructured":"Huebner, M., & Becker, J. (2006). Dynamic and partial FPGA self-reconfiguration using real-time LUT-based network-on-chip adaptive topologies for Xilinx FPGAs. Journal Integrated Circuits and Systems, 1(4)."},{"key":"607_CR28","unstructured":"Ullmann, M., H\u00fcbner, M., Grimm, B., & Becker, J. (2004). An FPGA run-time system for dynamic on-demand reconfiguration. Proceedings of the International Parallel and Distributed Processing Symposium."},{"issue":"2","key":"607_CR29","doi-asserted-by":"crossref","first-page":"438","DOI":"10.1109\/JPROC.2006.888404","volume":"95","author":"J Becker","year":"2007","unstructured":"Becker, J., H\u00fcbner, M., Hettich, G., Constapel, R., Eisenmann, J., & Luka, J. (2007). Dynamic and partial FPGA exploitation. Proceedings of the IEEE, 95(2), 438\u2013452.","journal-title":"Proceedings of the IEEE"},{"key":"607_CR30","doi-asserted-by":"crossref","unstructured":"Bobda, C., Majer, A., Ahmadinia, A., Haller, T., Linarth, A., & Teich, J. (2005). The Erlangen slot machine: increasing flexibility in FPGA-based reconfigurable platforms. Proceeding of the IEEE International Conference on Field-Programmable Technology, pp. 37\u201342.","DOI":"10.1109\/FPT.2005.1568522"},{"issue":"1","key":"607_CR31","doi-asserted-by":"crossref","first-page":"15","DOI":"10.1007\/s11265-006-0017-6","volume":"47","author":"M Majer","year":"2007","unstructured":"Majer, M., Teich, J., Ahmadinia, A., & Bobda, C. (2007). The Erlangen slot machine: a dynamically reconfigurable FPGA-based computer. The Journal of VLSI Signal Processing, 47(1), 15\u201331.","journal-title":"The Journal of VLSI Signal Processing"},{"issue":"11","key":"607_CR32","doi-asserted-by":"crossref","first-page":"1363","DOI":"10.1109\/TC.2004.104","volume":"53","author":"S Vassiliadis","year":"2004","unstructured":"Vassiliadis, S., Gaydadjiev, G., & Kuzmanov, G. (2004). The MOLEN polymorphic processor. IEEE Transactions on Computers, 53(11), 1363\u20131375.","journal-title":"IEEE Transactions on Computers"},{"key":"607_CR33","doi-asserted-by":"crossref","first-page":"192","DOI":"10.1007\/978-3-540-27776-7_21","volume":"3133","author":"GK Kuzmanov","year":"2004","unstructured":"Kuzmanov, G. K., Gaydadjiev, G. N., & Vassiliadis, S. (2004). The Virtex II Pro\u2122 MOLEN processor. Proceedings of the International Workshop on Computer Systems: Architectures, Modelling, and Simulation, LNCS 3133, 192\u2013202.","journal-title":"Proceedings of the International Workshop on Computer Systems: Architectures, Modelling, and Simulation, LNCS"},{"key":"607_CR34","doi-asserted-by":"crossref","unstructured":"Panainte, E. M., Bertels, K., & Vassiliadis, S. (2007). The Molen compiler for reconfigurable processors. ACM Transactions in Embedded Computing Systems, 6(1).","DOI":"10.1145\/1210268.1210274"},{"key":"607_CR35","doi-asserted-by":"crossref","first-page":"11","DOI":"10.1007\/978-3-540-27776-7_2","volume":"3133","author":"G Kuzmanov","year":"2003","unstructured":"Kuzmanov, G., Gaydadjiev, G. N., & Vassiliadis, S. (2003). Loading rm-code: design considerations. Proceedings of the International Workshop on Computer Systems: Architectures, Modeling, and Simulation, LNCS 3133, pp. 11\u201319.","journal-title":"Proceedings of the International Workshop on Computer Systems: Architectures, Modeling, and Simulation, LNCS"},{"key":"607_CR36","unstructured":"Altera Corp. (2003). Reconfiguring Excalibur devices under processor control. Application Note 298."},{"key":"607_CR37","unstructured":"Altera Corp. (2002). Excalibur devices hardware reference manual. Reference Manual."},{"key":"607_CR38","unstructured":"Atmel Corp. (2001). AT94K series configuration. Application Note 2313."},{"key":"607_CR39","unstructured":"Atmel Corp. (2001). AT94K series Cache Logic\u2122 (mode 4) configuration. Application Note 2323."},{"key":"607_CR40","doi-asserted-by":"crossref","unstructured":"Paulsson, K., H\u00fcbner, M., Auer, G., Dreschmann, M., Chen, L., & Becker, J. (2007) Implementation of a virtual internal configuration access port (JCAP) for enabling partial self-reconfiguration on Xilinx Spartan III FPGAs. Proceedings of the international conference on field programmable logic and applications, pp. 351\u2013356.","DOI":"10.1109\/FPL.2007.4380671"},{"key":"607_CR41","doi-asserted-by":"crossref","unstructured":"Gonzalez, I., Aguayo, E., & Lopez-Buedo, S. (2007). Self-reconfigurable embedded systems on low-cost FPGAs. IEEE MICRO, 49\u201357.","DOI":"10.1109\/MM.2007.72"},{"key":"607_CR42","unstructured":"Bayar, S., & Yurdakul, A. (2008). Dynamic partial self-reconfiguration on Spartan-III FPGAs via a parallel configuration access port (PCAP). Proceedings of HiPEAC workshop on reconfigurable computing, pp. 1\u201310."},{"key":"607_CR43","unstructured":"M\u00f6ller, L., Grehs, I., Carvalho, E., Soares, R., Calazans, N., & Moraes, F. (2007). A NoC-based infrastructure to enable dynamic self reconfigurable system. Proceedings of the 3rd workshop on reconfigurable communication-centric systems-on-chip, pp. 23\u201330."},{"key":"607_CR44","unstructured":"Van der Bok, K., Chaves, R., Kuzmanov, G., Sousa, L., & Van Genderen, A. (2007). Dynamic FPGA reconfigurations with run-time region delimitation. Proceedings of the 18th annual workshop on circuits, systems and signal processing, pp. 201\u2013207."},{"key":"607_CR45","doi-asserted-by":"crossref","unstructured":"Claus, C., M\u00fcller, F. H., Zeppenfeld, J., & Stechele, W. (2007). A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration. IEEE Parallel and Distributed Processing Symposium.","DOI":"10.1109\/IPDPS.2007.370362"},{"key":"607_CR46","unstructured":"Xilinx Inc. (2004). OPB HWICAP, Datasheet 280."},{"key":"607_CR47","unstructured":"Xilinx Inc. (2010). LogiCORE IP XPS HWICAP (v5.00a), Datasheet 586."},{"key":"607_CR48","doi-asserted-by":"crossref","unstructured":"H\u00fcbner, M., G\u00f6hringer, D., Noguera, J, & Becker, J. (2010). Fast dynamic and partial reconfiguration data path with low hardware overhead on Xilinx FPGAs. Proceedings of the IPDPS Reconfigurable Architectures Workshop, pp. 1\u20138.","DOI":"10.1109\/IPDPSW.2010.5470736"},{"key":"607_CR49","doi-asserted-by":"crossref","unstructured":"Claus, C., Zhang, B., Stechele, W., Braun, L., H\u00fcbner, M., & Becker, J., (2008). A multi-platform controller allowing for maximum dynamic partial reconfiguration throughput. Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 535\u2013538.","DOI":"10.1109\/FPL.2008.4630002"},{"key":"607_CR50","doi-asserted-by":"crossref","unstructured":"Liu, M., Kuehn, W., Lu, Z., & Jantsch, A. (2009). Run-time partial reconfiguration speed investigation and architectural design space exploration. Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 498\u2212502.","DOI":"10.1109\/FPL.2009.5272463"},{"key":"607_CR51","doi-asserted-by":"crossref","unstructured":"Manet, P., Maufroid, D., Tosi, L., Gailliard, G., Mulertt, O., Di Ciano, M., et al. (2008). An evaluation of dynamic partial reconfiguration for signal and image processing in professional electronics applications. EURASIP Journal on Embedded Systems, 1\u201311.","DOI":"10.1155\/2008\/367860"},{"key":"607_CR52","doi-asserted-by":"crossref","unstructured":"Nabina, A., & Nu\u00f1ez-Ya\u00f1ez, J. L. (2010). Dynamic reconfiguration optimisation with streaming data decompression. Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 602\u2013607.","DOI":"10.1109\/FPL.2010.118"},{"key":"607_CR53","unstructured":"Liu, S., Pittman, R. N., Forin, A. (2009). Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller, Microsoft Research, Technical Report MSR-TR-2009-150, pp. 1\u201333."},{"key":"607_CR54","unstructured":"Delorme, J., Nafkha, A., Leray, P., & Moy, C. (2009). New OPBHWICAP interface for realtime partial reconfiguration of FPGA, Proceedings of the International Conference on Reconfigurable Computing and FPGAs, pp. 386\u2013391."},{"key":"607_CR55","doi-asserted-by":"crossref","unstructured":"Shelburne, M., Patterson, C., Athanas, P., Jones, M., Martin, B., Fong, R. (2008). MetaWire: using FPGA configuration circuitry to emulate a network-on-chip. Proceedings of the International Conference on Field Programmable Logic and Applications, pp. 257\u2013262.","DOI":"10.1109\/FPL.2008.4629941"},{"key":"607_CR56","unstructured":"Claus, C., Ahmed, R., Altenried, F., Stechele, W. (2010). Towards rapid dynamic partial reconfiguration in video-based driver assistance systems, Proceedings of the International Symposium on Applied Reconfigurable Computing, LNCS 5992, Springer, pp. 55\u201367."},{"key":"607_CR57","unstructured":"Claus, C., Altenried, F., Stechele, W. (2010). Dynamic partial reconfiguration of Xilinx FPGAs lets system adapt on the fly. Xcell Journal, (70), 18\u201323."},{"key":"607_CR58","doi-asserted-by":"crossref","unstructured":"Claus, C., Zeppenfeld, J., M\u00fcller, F., Stechele, W. (2007). Using partial-run-time reconfigurable hardware to accelerate video processing in driver assistance systems. Processings of Design, Automation, and Test in Europe Conference, pp. 498\u2013503.","DOI":"10.1109\/DATE.2007.364642"},{"issue":"3","key":"607_CR59","first-page":"181","volume":"49","author":"C Claus","year":"2007","unstructured":"Claus, C., Stechele, W., & Herkersdorf, A. (2007). Autovision\u2014a run-time reconfigurable MPSoC architecture for future driver assistance systems. Information Technology Journal, 49(3), 181\u2013187.","journal-title":"Information Technology Journal"},{"key":"607_CR60","unstructured":"Platzner, M., Teich, J., Wehn, N. (eds.) (2010). Dynamically reconfigurable systems - Architectures, design methods and applications, Springer, pp. 375\u2013394."},{"issue":"12","key":"607_CR61","doi-asserted-by":"crossref","first-page":"991","DOI":"10.1109\/TCSII.2010.2087970","volume":"57","author":"M Fons","year":"2010","unstructured":"Fons, M., Fons, F., & Cant\u00f3, E. (2010). Fingerprint image processing acceleration through run-time reconfigurable hardware. IEEE Transactions on Circuits and Systems II: Express Briefs, 57(12), 991\u2013995.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"607_CR62","doi-asserted-by":"crossref","unstructured":"Fons, M., Fons, F., Cant\u00f3, E. (2010). Biometrics-based consumer applications driven by reconfigurable hardware architectures. Future Generation Computer Systems, doi: 10.1016\/j.future.2010.11.007 .","DOI":"10.1016\/j.future.2010.11.007"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0607-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-011-0607-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0607-9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,13]],"date-time":"2019-06-13T23:10:43Z","timestamp":1560467443000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-011-0607-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,8,10]]},"references-count":62,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2012,2]]}},"alternative-id":["607"],"URL":"https:\/\/doi.org\/10.1007\/s11265-011-0607-9","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2011,8,10]]}}}