{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,18]],"date-time":"2025-11-18T12:14:13Z","timestamp":1763468053851,"version":"3.38.0"},"reference-count":34,"publisher":"Springer Science and Business Media LLC","issue":"2","license":[{"start":{"date-parts":[[2011,12,29]],"date-time":"2011-12-29T00:00:00Z","timestamp":1325116800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2012,11]]},"DOI":"10.1007\/s11265-011-0650-6","type":"journal-article","created":{"date-parts":[[2011,12,28]],"date-time":"2011-12-28T19:23:28Z","timestamp":1325100208000},"page":"173-188","source":"Crossref","is-referenced-by-count":15,"title":["Instruction Cache Locking for Embedded Systems using Probability Profile"],"prefix":"10.1007","volume":"69","author":[{"given":"Tiantian","family":"Liu","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Minming","family":"Li","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chun Jason","family":"Xue","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2011,12,29]]},"reference":[{"key":"650_CR1","doi-asserted-by":"crossref","unstructured":"Sarkar, V. (1989). Determining average program execution times and their variance. In ACM SIGPLAN 1989 Conference on Programming language design and implementation, (pp. 298\u2013312).","DOI":"10.1145\/73141.74845"},{"key":"650_CR2","unstructured":"Guo, X., Boubekeur, M., McEnery, J., & Hickey, D. (2007). ACET based scheduling of soft real-time systems: An approach to optimise resource budgeting. In International Journal of Computers and Communications, (Issue 3, Vol. 1, pp. 82\u201389)."},{"key":"650_CR3","unstructured":"ARM. http:\/\/www.arm.com\/ ."},{"key":"650_CR4","unstructured":"MIPS. http:\/\/www.mips.com\/ ."},{"key":"650_CR5","unstructured":"Moto. http:\/\/www.motorola.com\/ ."},{"key":"650_CR6","doi-asserted-by":"crossref","unstructured":"Anand, K., & Barua, R. (2009). Instruction cache locking inside a binary rewriter. In Proceedings of the International Conference on Compilers Architectures and Synthesis for Embedded Systems (CASES09), (pp. 185\u2013194).","DOI":"10.1145\/1629395.1629422"},{"key":"650_CR7","doi-asserted-by":"crossref","unstructured":"Liang, Y., & Mitra, T. (2010). Instruction cache locking using temporal reuse profile. In Proceedings of the 47th Design Automation Conference (DAC10), (pp. 244\u2013340).","DOI":"10.1145\/1837274.1837362"},{"key":"650_CR8","doi-asserted-by":"crossref","unstructured":"Buck, B., & Hollingsworth, J. K. (2000). An API for runtime code patching. In International Journal of High Performance Computing Applications, 14(4), 317\u2013329.","DOI":"10.1177\/109434200001400404"},{"key":"650_CR9","doi-asserted-by":"crossref","unstructured":"Puaut, I., & Decotigny, D. (2002). Low-complexity algorithms for static cache locking in multitasking hard real-time systems. In Proceedings of the 23rd IEEE Real-Time Systems Symposium (RTSS02), (pp. 114\u2013123).","DOI":"10.1109\/REAL.2002.1181567"},{"key":"650_CR10","unstructured":"Arnaud, A., & Puaut, I. (2006). Dynamic instruction cache locking in hard real-time systems. In Proceedings of the 14th International Conference on Real-Time and Network Systems (RTNS06)."},{"key":"650_CR11","doi-asserted-by":"crossref","unstructured":"Campoy, A. M., Ivars, A.\u00a0P., Rodriguez, F., & Busquets Mataix, J.\u00a0V. (2003). Static use of locking caches vs dynamic use of locking caches for real-time systems. In IEEE Canadian Conference on Electrical and Computer Engineering, (pp. 1283\u20131286).","DOI":"10.1109\/CCECE.2003.1226134"},{"key":"650_CR12","doi-asserted-by":"crossref","unstructured":"Campoy, A. M., Ivars, A.\u00a0P., & Busquets Mataix, J.\u00a0V. (2002). Dynamic use of locking caches in multitask, preemptive real-time systems. In 15th Triennial World Congress.","DOI":"10.3182\/20020721-6-ES-1901.00974"},{"key":"650_CR13","doi-asserted-by":"crossref","unstructured":"Falk, H., Plazar, S., & Theiling, H. (2007). Compile-time decided instruction cache locking using worst-case execution paths. In Proceedings of the 5th IEEE\/ACM international conference on Hardware\/software codesign and system synthesis (CODE+ISSS07), (pp. 143\u2013148).","DOI":"10.1145\/1289816.1289853"},{"key":"650_CR14","doi-asserted-by":"crossref","unstructured":"Liu, T., Li, M., & Xue, C. J. (2009). Minimizing WCET for Real-time Embedded Systems via Static Instruction Cache Locking. In Proceedings of the 15th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS09), (pp. 35\u201344).","DOI":"10.1109\/RTAS.2009.11"},{"key":"650_CR15","unstructured":"Kandemir, M., Ramanujam, J., Irwin, M.\u00a0J., Vijaykrishnan, N., Kadayil, I., & Parikh, A. (2001). Dynamic management of scratchpad memory space. In Proceedings of the 38th Design Automation Conference (DAC01), (pp. 690\u2013695)."},{"key":"650_CR16","doi-asserted-by":"crossref","unstructured":"Udayakumaran,S., & Barua, R. (2003). Compiler-decided dynamic memory allocation for scratch-pad based embedded systems. In Proceedings of the International Conference on Compilers, Architectures and Synthesis for Embedded Systems, (pp. 276\u2013286).","DOI":"10.1145\/951710.951747"},{"key":"650_CR17","doi-asserted-by":"crossref","unstructured":"Puaut, I., & Pais, C. (2007). Scratchpad memories vs locked caches in hard real-time systems: a quantitative comparison. In Proceedings of the conference on Design, Automation and Test in Europe (DATE07), (pp. 1484\u20131489).","DOI":"10.1109\/DATE.2007.364510"},{"key":"650_CR18","doi-asserted-by":"crossref","unstructured":"Liang, Y., & Mitra, T. (2008). Cache modeling in probabilistic execution time analysis. In Proceedings of the 45th Design Automation Conference (DAC08), (pp. 319\u2013324).","DOI":"10.1145\/1391469.1391551"},{"issue":"2","key":"650_CR19","doi-asserted-by":"crossref","first-page":"452","DOI":"10.1145\/1067915.1067924","volume":"4","author":"P Petrov","year":"2005","unstructured":"Petrov, P., & Orailoglu, A. (2005). A reprogrammable customization framework for efficient branch resolution embedded processors. ACM Transactions on Embedded Computing Systems, 4(2), 452\u2013468.","journal-title":"ACM Transactions on Embedded Computing Systems"},{"key":"650_CR20","doi-asserted-by":"crossref","unstructured":"Xue, C. J., Sha, E. H. -M., Shao, Z., & Qiu, M. (2008). Effective loop partitioning and scheduling under memory and register dual constraints. In Proceedings of the 40th Design, Automation and Test in Europe (DATE08) (pp. 1202\u20131207).","DOI":"10.1109\/DATE.2008.4484842"},{"key":"650_CR21","doi-asserted-by":"crossref","unstructured":"Qiu, M., Xue, C., Shao, Z., & Sha, E. H. -M. (2007). Energy minimization with soft real-time and DVS for uniprocessor and multiprocessor embedded systems. In Proceedings of the 39th Design, Automation and Test in Europe (DATE07) (pp. 1641\u20131646).","DOI":"10.1109\/DATE.2007.364537"},{"issue":"1","key":"650_CR22","doi-asserted-by":"crossref","first-page":"165","DOI":"10.1145\/1124713.1124724","volume":"11","author":"Z Shao","year":"2006","unstructured":"Shao, Z., Xiao, B., Xue, C., Zhuge, Q., Sha, E. H. -M. (2006). Loop scheduling with timing and switching-activity minimization for VLIW DSP. ACM Transactions on Design Automation of Electronic Systems, 11(1), 165\u2013185.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"650_CR23","unstructured":"Intel. http:\/\/www.intel.com\/design\/intelxscale ."},{"key":"650_CR24","unstructured":"IDT. http:\/\/www.idt.com\/ ."},{"key":"650_CR25","doi-asserted-by":"crossref","unstructured":"Gordon-Ross, A., Vahid, F., & Dutt, N. (2005). A first look at the interplay of code reordering and configurable caches. In Proceedings of the 15th ACM Great Lakes symposium on VLSI, (pp. 416\u2013421).","DOI":"10.1145\/1057661.1057760"},{"issue":"4","key":"650_CR26","doi-asserted-by":"crossref","first-page":"437","DOI":"10.3233\/EMC-2005-00045","volume":"1","author":"C Guillon","year":"2004","unstructured":"Guillon, C., Rastello, F., Bidault, T., & Bouchez, F. (2004). Procedure placement using temporal-ordering information: dealing with code size expansion. Journal of Embedded Computing, 1(4), 437\u2013459.","journal-title":"Journal of Embedded Computing"},{"issue":"4","key":"650_CR27","doi-asserted-by":"crossref","first-page":"335","DOI":"10.1145\/1113841.1113842","volume":"2","author":"W Zhao","year":"2005","unstructured":"Zhao, W., Whalley, D., Healy, C., & Mueller, F. (2005). Improving WCET by Applying a WC Code-Positioning Optimization. ACM Transactions on Architecture and Code Optimization, 2(4), 335\u2013365.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"key":"650_CR28","unstructured":"StreamIt. http:\/\/www.cag.lcs.mit.edu\/streamit\/shtml\/benchmarks.shtml ."},{"key":"650_CR29","unstructured":"SimpleScalar. http:\/\/www.simplescalar.com\/ ."},{"key":"650_CR30","doi-asserted-by":"crossref","first-page":"52","DOI":"10.1007\/s11241-008-9062-5","volume":"41","author":"S Chakraborty","year":"2009","unstructured":"Chakraborty, S., Mitra, T., Roychoudhury, A., & Thiele, L. (2009). Cache-aware timing analysis of streaming applications. Real-Time Syst, 41, 52\u201385.","journal-title":"Real-Time Syst"},{"key":"650_CR31","unstructured":"Martello, S., & Toth, P. (1990). Knapsack Problems: Algorithms and Computer Implementation. John Wiley and Sons."},{"key":"650_CR32","unstructured":"MRTC. http:\/\/www.mrtc.mdh.se\/projects\/wcet\/home.html ."},{"key":"650_CR33","unstructured":"MiBench. http:\/\/www.eecs.umich.edu\/mibench\/ ."},{"issue":"2","key":"650_CR34","doi-asserted-by":"crossref","first-page":"217","DOI":"10.1023\/A:1008145215849","volume":"18","author":"F Mueller","year":"2000","unstructured":"Mueller, F. (2000). Timing analysis for instruction caches. Real-Time Systems, 18(2), 217\u2013247.","journal-title":"Real-Time Systems"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0650-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-011-0650-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-011-0650-6","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,17]],"date-time":"2025-03-17T00:42:30Z","timestamp":1742172150000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-011-0650-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,12,29]]},"references-count":34,"journal-issue":{"issue":"2","published-print":{"date-parts":[[2012,11]]}},"alternative-id":["650"],"URL":"https:\/\/doi.org\/10.1007\/s11265-011-0650-6","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2011,12,29]]}}}