{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,5,21]],"date-time":"2025-05-21T05:28:32Z","timestamp":1747805312343},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"1","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2013,1]]},"DOI":"10.1007\/s11265-012-0656-8","type":"journal-article","created":{"date-parts":[[2012,2,28]],"date-time":"2012-02-28T02:49:10Z","timestamp":1330397350000},"page":"21-37","source":"Crossref","is-referenced-by-count":10,"title":["Differential Time Signaling Data-Link Architecture"],"prefix":"10.1007","volume":"70","author":[{"given":"Mostafa","family":"Rashdan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Abdel","family":"Yousif","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"James","family":"Haslett","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Brent","family":"Maundy","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2012,2,29]]},"reference":[{"key":"656_CR1","doi-asserted-by":"crossref","first-page":"51","DOI":"10.1109\/4.974545","volume":"37","author":"O-C Chen","year":"2002","unstructured":"Chen, O.-C., & Sheen, R.-B. (2002). A power-efficient wide-range phase-locked loop. IEEE Journal of Solid-State Circuits, 37, 51\u201362.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"656_CR2","doi-asserted-by":"crossref","first-page":"231","DOI":"10.1109\/TVLSI.2007.893588","volume":"15","author":"L Zhang","year":"2007","unstructured":"Zhang, L., Wilson, J., Bashirullah, R., Luo, L., Xu, J., & Franzon, P. (2007). Voltage-mode driver preemphasis technique for on-chip global buses. IEEE Transaction on Very Large Scale Integration System (VLSI) (USA), 15, 231\u2013236.","journal-title":"IEEE Transaction on Very Large Scale Integration System (VLSI) (USA)"},{"key":"656_CR3","doi-asserted-by":"crossref","first-page":"178","DOI":"10.1109\/TCSII.2010.2041809","volume":"57","author":"S-Y Kao","year":"2010","unstructured":"Kao, S.-Y., & Liu, S.-I. (2010). A 1.62\/2.7-Gb\/s adaptive transmitter with two-tap preemphasis using a propagation-time detector. IEEE Transaction on Circuits and Systems II, Express Briefs (USA), 57, 178\u2013182.","journal-title":"IEEE Transaction on Circuits and Systems II, Express Briefs (USA)"},{"key":"656_CR4","doi-asserted-by":"crossref","first-page":"319","DOI":"10.1109\/TCSII.2010.2047316","volume":"57","author":"S-Y Kao","year":"2010","unstructured":"Kao, S.-Y., & Liu, S.-I. (2010). A 20-Gb\/s transmitter with adaptive preemphasis in 65-nm CMOS technology. IEEE Transaction on Circuits and Systems II, Express Briefs (USA), 57, 319\u2013323.","journal-title":"IEEE Transaction on Circuits and Systems II, Express Briefs (USA)"},{"key":"656_CR5","first-page":"170","volume-title":"A 20Gb\/s 40mW equalizer in 90nm CMOS technology","author":"SA Ibrahim","year":"2010","unstructured":"Ibrahim, S. A., & Razavi, B. (2010). A 20Gb\/s 40mW equalizer in 90nm CMOS technology (pp. 170\u2013171). San Francisco: Proc. ISSCC Dig. Tech. Papers."},{"key":"656_CR6","first-page":"162","volume-title":"A 16Gb\/s 1st-tap FFE and 3-tap DFE in 90nm CMOS","author":"H Sugita","year":"2010","unstructured":"Sugita, H., Sunaga, K., Yamaguchi, K., & Mizuno, M. (2010). A 16Gb\/s 1st-tap FFE and 3-tap DFE in 90nm CMOS (pp. 162\u2013163). San Francisco: Proc. ISSCC Dig. Tech. Papers."},{"key":"656_CR7","doi-asserted-by":"crossref","first-page":"1058","DOI":"10.1109\/TIM.2007.915134","volume":"57","author":"C-Y Yang","year":"2008","unstructured":"Yang, C.-Y., & Lee, Y. (2008). A PWM and PAM signaling hybrid technology for serial-link transceivers. IEEE Transaction Instrumentation and Measurement (USA), 57, 1058\u20131070.","journal-title":"IEEE Transaction Instrumentation and Measurement (USA)"},{"key":"656_CR8","first-page":"934","volume":"E79-C","author":"T Yamauchi","year":"1996","unstructured":"Yamauchi, T., Morooka, Y., & Ozaki, H. (1996). A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for as-memory. IEICE Transactions and Electronics (Japan), E79-C, 934\u2013941.","journal-title":"IEICE Transactions and Electronics (Japan)"},{"key":"656_CR9","doi-asserted-by":"crossref","first-page":"1498","DOI":"10.1109\/4.953478","volume":"36","author":"W-H Chen","year":"2001","unstructured":"Chen, W.-H., Dehang, G.-K., Chen, J.-W., & Liu, S.-I. (2001). A CMOS 400-Mb\/s serial link for as-memory systems using a PWM scheme. IEEE Journal of Solid-State Circuits (USA), 36, 1498\u20131505.","journal-title":"IEEE Journal of Solid-State Circuits (USA)"},{"key":"656_CR10","first-page":"531","volume-title":"A new time-based architecture for serial communication links. IEEE 16th Int. Conf. on Electronics","author":"M Rashdan","year":"2009","unstructured":"Rashdan, M., Yousif, J., Haslett, A., & Maundy, B. (2009). A new time-based architecture for serial communication links. IEEE 16th Int. Conf. on Electronics (pp. 531\u2013534). Hammamat: Circuits and Systems (ICECS)."},{"key":"656_CR11","first-page":"3977","volume-title":"Data link design using time-based approach","author":"M Rashdan","year":"2010","unstructured":"Rashdan, M., Yousif, J., Haslett, A., & Maundy, B. (2010). Data link design using time-based approach (pp. 3977\u20133980). Paris: IEEE Int. Symp. on Circuits and Systems (ISCAS)."},{"key":"656_CR12","first-page":"1055","volume-title":"A low power and high speed ppm design for ultra wideband communications","author":"A Yousif","year":"2008","unstructured":"Yousif, A., Rashdan, M., Haslett, J., & Maundy, B. (2008). A low power and high speed ppm design for ultra wideband communications (pp. 1055\u20131058). Niagra falls: The Canadian Conf. on Electrical and Computer Engineering (CCECE)."},{"key":"656_CR13","doi-asserted-by":"crossref","unstructured":"Minas, N., Kinniment, D., Heron, K., & Russell G. (2007). A high resolution flash time-to-digital converter taking into account process variability. 13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC\u201907), pp. 168\u201377.","DOI":"10.1109\/ASYNC.2007.7"},{"key":"656_CR14","doi-asserted-by":"crossref","unstructured":"Levine, P., & Roberts, G. (2004). A high-resolution flash time-to-digital converter and calibration scheme. Proc. of the International Test Conference, pp. 1148\u201357.","DOI":"10.1109\/TEST.2004.1387389"},{"issue":"5","key":"656_CR15","doi-asserted-by":"crossref","first-page":"1574","DOI":"10.1109\/TNS.2007.903183","volume":"54","author":"A Yousif","year":"2007","unstructured":"Yousif, A., & Haslett, J. (2007). A fine resolution TDC architecture for next generation PET imaging. IEEE Transactions on Nuclear Science, 54(5), 1574\u20131582.","journal-title":"IEEE Transactions on Nuclear Science"},{"key":"656_CR16","unstructured":"Younis, A. et al. (2001). A low jitter, low power, CMOS 1.25-3.125 Gbps transceiver. Proc. of the 27th European Solid-State Circuits Conf. (ESSCIRC), Paris, France, pp. 148\u2013151."},{"issue":"9","key":"656_CR17","doi-asserted-by":"crossref","first-page":"1957","DOI":"10.1109\/JSSC.2005.848180","volume":"40","author":"V Balan","year":"2005","unstructured":"Balan, V., et al. (2005). A 4.8-6.4-Gb\/s serial link for backplane applications using decision feedback equalization. IEEE Journal of Solid-State Circuits, 40(9), 1957\u20131965.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"656_CR18","doi-asserted-by":"crossref","first-page":"3547","DOI":"10.1109\/JSSC.2009.2031021","volume":"44","author":"Y Hidaka","year":"2009","unstructured":"Hidaka, Y., et al. (2009). A 4-channel 1.25\u201310.3\u00a0Gb\/s backplane transceiver macro with 35\u00a0dB equalizer and sign-based zero-forcing adaptive control. IEEE Journal of Solid-State Circuits, 44, 3547\u20133559.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"656_CR19","first-page":"168","volume-title":"A 5Gbs transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65\u00a0nm CMOS","author":"H Yamaguchi","year":"2010","unstructured":"Yamaguchi, H., et al. (2010). A 5Gbs transceiver with an ADC-based feedforward CDR and CMA adaptive equalizer in 65\u00a0nm CMOS (pp. 168\u2013169). San Francisco: Proc. ISSCC Dig. Tech. Papers."},{"key":"656_CR20","unstructured":"Jikyung Jeong, J.L., & Burm, J. (2009). A CMOS 3.2 Gb\/s 4-PAM serial link transceiver. International SoC Design Conference (ISOCC 2009), pp. 408\u2013411."},{"key":"656_CR21","doi-asserted-by":"crossref","first-page":"1803","DOI":"10.1109\/JSSC.2006.876206","volume":"41","author":"A Abidi","year":"2006","unstructured":"Abidi, A. (2006). Phase noise and jitter in CMOS ring oscillators. IEEE Journal of Solid-State Circuits, 41, 1803\u20131816.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"656_CR22","unstructured":"Townsend, K. (2010). Interference-Mitigating TR-UWB Receiver. Ph.d. thesis. Calgary, Alberta, Canada: University of Calgary."},{"key":"656_CR23","unstructured":"Gilley, J. E. (2003). Bit-error rate simulation using Matlab. http:\/\/www.efjohnsontechnologies.com\/resources\/dyn \/files\/75831\/-fn\/bit-error-rate."},{"issue":"5","key":"656_CR24","doi-asserted-by":"crossref","first-page":"897","DOI":"10.1109\/TIM.2007.913760","volume":"57","author":"Y Fan","year":"2008","unstructured":"Fan, Y., & Zilic, Z. (2008). Ber testing of communication interfaces. IEEE Transactions on Instrumentation and Measurement, 57(5), 897\u2013906.","journal-title":"IEEE Transactions on Instrumentation and Measurement"},{"key":"656_CR25","unstructured":"Lopez-Rivera, M. L. (2009). A 3.125 GB\/s 5-Tap CMOS Transversal equalizer. PhD thesis. Texas: AM University."},{"key":"656_CR26","doi-asserted-by":"crossref","unstructured":"Ramakrishnan, V., & Balsara, P. T. (2006). A wide-range, high-resolution, compact, CMOS time to digital converter. Proceedings of the IEEE International Conference on VLSI Design, Hyderabad, India, pp. 197\u2013202.","DOI":"10.1109\/VLSID.2006.28"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/www.springerlink.com\/index\/pdf\/10.1007\/s11265-012-0656-8","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,24]],"date-time":"2019-06-24T16:53:47Z","timestamp":1561395227000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-012-0656-8"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2012,2,29]]},"references-count":26,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2013,1]]}},"alternative-id":["656"],"URL":"https:\/\/doi.org\/10.1007\/s11265-012-0656-8","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2012,2,29]]}}}