{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,8,12]],"date-time":"2025-08-12T22:14:23Z","timestamp":1755036863612},"reference-count":15,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2013,7,20]],"date-time":"2013-07-20T00:00:00Z","timestamp":1374278400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2014,12]]},"DOI":"10.1007\/s11265-013-0810-y","type":"journal-article","created":{"date-parts":[[2013,7,19]],"date-time":"2013-07-19T03:11:26Z","timestamp":1374203486000},"page":"281-287","source":"Crossref","is-referenced-by-count":1,"title":["Area-Efficient Parallel Syndrome Generators for Linear Block Codes"],"prefix":"10.1007","volume":"77","author":[{"given":"Junho","family":"Cho","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jonghong","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Wonyong","family":"Sung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2013,7,20]]},"reference":[{"key":"810_CR1","unstructured":"Chen, B., Zhang, X., Wang, Z. (2008). Error correction for multi-level NAND flash memory using Reed-Solomon codes. In Proceedings IEEE workshop on signal processing systems (pp. 94\u201399)."},{"key":"810_CR2","unstructured":"Chen, Y., & Parhi, K.K. (2004). Area efficient parallel decoder architecture for long BCH codes. In Proceedings international conference on acoustics, speech, and signal processing (ICASSP) (Vol. 5, pp. V\u201373\u2013V\u201376)."},{"issue":"5","key":"810_CR3","doi-asserted-by":"crossref","first-page":"427","DOI":"10.1109\/TCSII.2007.914898","volume":"55","author":"J Cho","year":"2008","unstructured":"Cho, J., & Sung, W. (2008). Strength-reduced parallel Chien search architecture for strong BCH codes. IEEE Transactions Circuits System II, 55(5), 427\u2013431.","journal-title":"IEEE Transactions Circuits System II"},{"issue":"2","key":"810_CR4","doi-asserted-by":"crossref","first-page":"288","DOI":"10.1109\/TVLSI.2003.810782","volume":"11","author":"H Lee","year":"2003","unstructured":"Lee, H. (2003). High-speed VLSI architecture for parallel Reed-Solomon decoder. IEEE Transactions VLSI System, 11(2), 288\u2013294.","journal-title":"IEEE Transactions VLSI System"},{"issue":"8","key":"810_CR5","doi-asserted-by":"crossref","first-page":"522","DOI":"10.1109\/TCSII.2011.2158709","volume":"58","author":"Y Lee","year":"2011","unstructured":"Lee, Y., Yoo, H., Park, I.C. (2011). Low-complexity parallel Chien search structure using two-dimensional optimization. IEEE Transactions Circuits System II, 58(8), 522\u2013526.","journal-title":"IEEE Transactions Circuits System II"},{"issue":"11","key":"810_CR6","first-page":"2330","volume":"45","author":"YM Lin","year":"2010","unstructured":"Lin, Y.M., Chen, C.L., Chang, H.C., Lee, C.Y. (2010). A 26.9 K 314.5 Mb\/s soft (32400,32208) BCH decoder chip for DVB-S2 system. IEEE Journal of Solid-State Circuits, 45(11), 2330\u20132340.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"810_CR7","doi-asserted-by":"crossref","unstructured":"Liu, W., Rho, J., Sung, W. (2006). Low-power high-throughput BCH error correction VLSI design for multi-level cell NAND flash memories. In Proceedings IEEE workshop on signal processing systems design and implementation (SIPS) (pp. 303\u2013308).","DOI":"10.1109\/SIPS.2006.352599"},{"key":"810_CR8","doi-asserted-by":"crossref","unstructured":"Park, J.I., Lee, K., Choi, C.S., Lee, H. (2009). High-speed low-complexity Reed-Solomon decoder using pipelined Berlekamp-Massey algorithm. In Proceedings international SoC design conference (ISOCC) (pp. 452\u2013455).","DOI":"10.1109\/SOCDC.2009.5423927"},{"issue":"2","key":"810_CR9","doi-asserted-by":"crossref","first-page":"151","DOI":"10.1109\/43.486662","volume":"15","author":"M Potkonjak","year":"1996","unstructured":"Potkonjak, M., Srivastava, M.B., Chandrakasan, A.P. (1996). Multiple constant multiplications: efficient and versatile framework and algorithms for exploring common subexpression elimination. IEEE Transaction Computer-Aided Design, 15(2), 151\u2013165.","journal-title":"IEEE Transaction Computer-Aided Design"},{"issue":"8","key":"810_CR10","doi-asserted-by":"crossref","first-page":"1003","DOI":"10.1109\/26.705396","volume":"46","author":"RM Pyndiah","year":"1998","unstructured":"Pyndiah, R.M. (1998). Near-optimum decoding of product codes: Block turbo codes. IEEE Transsaction Computations, 46(8), 1003\u20131010.","journal-title":"IEEE Transsaction Computations"},{"issue":"5","key":"810_CR11","doi-asserted-by":"crossref","first-page":"641","DOI":"10.1109\/92.953498","volume":"9","author":"DV Sarwate","year":"2001","unstructured":"Sarwate, D.V., & Shanbhag, N.R. (2001). High-speed architectures for Reed-Solomon decoders. IEEE Transactions VLSI System, 9(5), 641\u2013655.","journal-title":"IEEE Transactions VLSI System"},{"issue":"11","key":"810_CR12","doi-asserted-by":"crossref","first-page":"1565","DOI":"10.1109\/JSSC.2002.803931","volume":"37","author":"L Song","year":"2002","unstructured":"Song, L., Yu, M.L., Shaffer, M.S. (2002). 10- and 40-Gb\/s forward error correction devices for optical communications. IEEE Journal of Solid-State Circuits, 37(11), 1565\u20131573.","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"11","key":"810_CR13","doi-asserted-by":"crossref","first-page":"865","DOI":"10.1109\/TCSII.2009.2029144","volume":"56","author":"W Xueqiang","year":"2009","unstructured":"Xueqiang, W., Liyang, P., Dong, W., Chaohong, H., Runde, Z. (2009). A high-speed two-cell BCH decoder for error correcting in MLC NOR flash memories. IEEE Transactions Circuits System II, 56(11), 865\u2013869.","journal-title":"IEEE Transactions Circuits System II"},{"issue":"2","key":"810_CR14","doi-asserted-by":"crossref","first-page":"107","DOI":"10.1049\/el.2010.3260","volume":"47","author":"H Yoo","year":"2011","unstructured":"Yoo, H., Lee, Y., Park, I.C. (2011). Area-efficient syndrome calculation for strong BCH decoding. IET Electronics Letters, 47(2), 107\u2013108.","journal-title":"IET Electronics Letters"},{"key":"810_CR15","unstructured":"Zhang, B., Liu, D., Wang, S., Chen, X., Liu, H. (2010). Design and implementation of area-efficient DVB-S2 BCH decoder. In Proceedings international conference on computer engineering and technology (ICCET) (pp. V3\u2013179\u2013V3\u2013184)."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-013-0810-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-013-0810-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-013-0810-y","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,7,18]],"date-time":"2019-07-18T21:42:36Z","timestamp":1563486156000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-013-0810-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2013,7,20]]},"references-count":15,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2014,12]]}},"alternative-id":["810"],"URL":"https:\/\/doi.org\/10.1007\/s11265-013-0810-y","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2013,7,20]]}}}