{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,23]],"date-time":"2026-09-23T04:44:48Z","timestamp":1790138688101,"version":"4.0.1"},"reference-count":38,"publisher":"Springer Science and Business Media LLC","issue":"1","license":[{"start":{"date-parts":[[2016,2,9]],"date-time":"2016-02-09T00:00:00Z","timestamp":1454976000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2017,4]]},"DOI":"10.1007\/s11265-016-1106-9","type":"journal-article","created":{"date-parts":[[2016,2,8]],"date-time":"2016-02-08T21:25:01Z","timestamp":1454966701000},"page":"81-106","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":13,"title":["Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy"],"prefix":"10.1007","volume":"87","author":[{"given":"Francesca","family":"Palumbo","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Tiziana","family":"Fanni","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Carlo","family":"Sau","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Paolo","family":"Meloni","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"297","published-online":{"date-parts":[[2016,2,9]]},"reference":[{"key":"1106_CR1","doi-asserted-by":"crossref","unstructured":"Esmaeilzadeh, H., Blem, E., St. Amant, R., Sankaralingam, K., & Burger, D. (2011). Dark silicon and the end of multicore scaling. In Proceedings of the 38th annual international symposium on computer architecture (ISCA) (pp. 365\u2013 376).","DOI":"10.1145\/2000064.2000108"},{"key":"1106_CR2","unstructured":"Taylor, M.B. (2012). Is dark silicon useful? Harnessing the four horsemen of the coming dark silicon apocalypse. In ACM\/EDAC\/IEEE Design automation conference (DAC) (pp. 1131\u20131136)."},{"key":"1106_CR3","doi-asserted-by":"crossref","unstructured":"Herbert, S., & Marculescu, D. (2007). Analysis of dynamic voltage\/frequency scaling in chip-multiprocessors. In ACM\/IEEE International symposium on low power electronics and design (ISLPED) (pp. 38\u201343).","DOI":"10.1145\/1283780.1283790"},{"issue":"1","key":"1106_CR4","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/1952998.1952999","volume":"8","author":"S Eyerman","year":"2011","unstructured":"Eyerman, S., & Eeckhout, L. (2011). Fine-grained DVFS using on-chip regulators. ACM Transactions on Architecture and Code Optimization (TACO), 8(1), 1\u201324.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"1106_CR5","doi-asserted-by":"crossref","unstructured":"Arora, M., Manne, S., Eckert, Y., Paul, I., Jayasena, N., & Tullsen, D.M. (2014). A comparison of core power gating strategies implemented in modern hardware. In ACM SIGMETRICS \/ International conference on measurement and modeling of computer systems (SIGMETRICS) (pp. 559\u2013560).","DOI":"10.1145\/2591971.2592017"},{"key":"1106_CR6","unstructured":"Jeff, B. (2012). Advances in big.little technology for power and energy savings. In ARM White paper."},{"key":"1106_CR7","unstructured":"Power Forward Initiative (2009). A Practical Guide to Low Power Design."},{"key":"1106_CR8","unstructured":"Wingard, D. (2013). Noc power-management advantages. In Keynote talks at IP-soc conference and exibition."},{"key":"1106_CR9","doi-asserted-by":"crossref","unstructured":"Sau, C., Raffo, L., Palumbo, F., Bezati, E., Casale-Brunet, S., & Mattavelli, M. (2014). Automated design flow for coarse-grained reconfigurable platforms: an rvc-cal multi-standard decoder use-case. In Conference on embedded computer systems: architectures, Modeling, and Simulation (SAMOS XIV), IEEE (pp. 59\u201366).","DOI":"10.1109\/SAMOS.2014.6893195"},{"issue":"1","key":"1106_CR10","doi-asserted-by":"crossref","first-page":"233","DOI":"10.1007\/s11554-012-0284-3","volume":"9","author":"F Palumbo","year":"2014","unstructured":"Palumbo, F., Carta, N., Pani, D., Meloni, P., & Raffo, L. (2014). The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms. Journal of Real-Time Image Processing (JRTIP), 9(1), 233\u2013249.","journal-title":"Journal of Real-Time Image Processing (JRTIP)"},{"key":"1106_CR11","doi-asserted-by":"crossref","unstructured":"Carta, N., Sau, C., Pani, D., Palumbo, F., & Raffo, L. (2013). A Coarse-Grained reconfigurable approach for Low-Power spike sorting architectures. In IEEE\/EMBS International conference on neural engineering (NER) (pp. 439\u2013442).","DOI":"10.1109\/NER.2013.6695966"},{"key":"1106_CR12","unstructured":"Carta, N., Sau, C., Palumbo, F., Pani, D., & Raffo, L. (2013). A Coarse-Grained reconfigurable wavelet denoiser exploiting the Multi-Dataflow composer tool. In Conference on design and architectures for signal and image processing (DASIP) (pp. 141\u2013148)."},{"key":"1106_CR13","unstructured":"ISO\/IEC 23001-4 (2009). MPEG-part 4: Codec configuration representation."},{"key":"1106_CR14","unstructured":"ISO\/IEC 23002-4 (2010). MPEG video tech.\u2014Part 4: Video tool library."},{"issue":"1","key":"1106_CR15","doi-asserted-by":"crossref","first-page":"36","DOI":"10.1049\/iet-cdt.2014.0089","volume":"9","author":"F Palumbo","year":"2014","unstructured":"Palumbo, F., Sau, C., & Raffo, L. (2014). Coarse-grained reconfiguration: dataflow-based power management. In IET Computers & Digital Techniques, 9(1), 36\u201348.","journal-title":"In IET Computers & Digital Techniques"},{"key":"1106_CR16","doi-asserted-by":"crossref","unstructured":"Palumbo, F., Sau, C., & Raffo, L. (2014). Power-awarness in coarse-grained reconfigurable designs: a dataflow based strategy. In IEEE Workshop on signal processing systems (siPS), IEEE (pp. 1\u20136).","DOI":"10.1109\/SiPS.2014.6986104"},{"key":"1106_CR17","unstructured":"Kahn, G. (1974). The semantics of a simple language for parallel programming. In International Conference on Information Processing (pp. 471\u2013475)."},{"key":"1106_CR18","doi-asserted-by":"crossref","unstructured":"Lee, E.A., & Parks, T. (1995). Dataflow process networks. In Proceedings of the IEEE (pp. 773\u2013799).","DOI":"10.1109\/5.381846"},{"key":"1106_CR19","unstructured":"Eker, J., & Janneck, J.W. (2003). Cal Language Report Specification of the Cal Actor Language. Technical report EECS Department, University of California, Berkeley."},{"key":"1106_CR20","unstructured":"Open RVC-CAL Compiler. http:\/\/orcc.sourceforge.net\/ ."},{"key":"1106_CR21","doi-asserted-by":"crossref","unstructured":"Bezati, E., Mattavelli, M., & Janneck, J. (2013). High-Level Synthesis of dataflow programs for signal processing systems. In International symposium on image and signal processing and analysis (ISPA) (pp. 750\u2013754).","DOI":"10.1109\/ISPA.2013.6703837"},{"key":"1106_CR22","unstructured":"Casale-Brunet, S., Mattavelli, M., & Janneck, J. W. (2013). Turnus: a design exploration framework for dataflow system design. In International symposium on circuits and systems (ISCAS) (pp. 654\u2013654)."},{"key":"1106_CR23","doi-asserted-by":"crossref","first-page":"135","DOI":"10.1007\/s11265-006-7512-7","volume":"44","author":"SM Carta","year":"2006","unstructured":"Carta, S.M., Pani, D., & Raffo, L. (2006). Reconfigurable coprocessor for multimedia application domain. Journal of VLSI Signal Processing Systems, 44, 135\u2013152.","journal-title":"Journal of VLSI Signal Processing Systems"},{"key":"1106_CR24","first-page":"1","volume":"14","author":"VV Kumar","year":"2006","unstructured":"Kumar, V.V., & Lach, J. (2006). Highly flexible multimode digital signal processing systems using adaptable components and controllers. EURASIP Journal on Applied Signal Processing, 14, 1\u20139.","journal-title":"EURASIP Journal on Applied Signal Processing"},{"key":"1106_CR25","doi-asserted-by":"crossref","unstructured":"Palumbo, F., Pani, D., Manca, E., Raffo, L., Mattavelli, M., & RVC, G. Roquier. (2010). A multi-decoder CAL Composer tool. In Conference on design and architectures for signal and image processing (DASIP) (pp. 144\u2013151).","DOI":"10.1109\/DASIP.2010.5706258"},{"key":"1106_CR26","doi-asserted-by":"crossref","unstructured":"Palumbo, F., Carta, N., & Raffo, L. (2011). The Multi-Dataflow Composer tool: a runtime reconfigurable HDL platform composer. In Conference on design and architectures for signal and image processing (DASIP) (pp. 178\u2013185).","DOI":"10.1109\/DASIP.2011.6136876"},{"key":"1106_CR27","unstructured":"Wipliez, M., Siret, N., Carta, N., Palumbo, F., & Raffo, L. (2012). Design IP faster: introducing the C\u02dchigh-level language. In IP-SOC: IP-Embedded System Conference and Exhibition."},{"key":"1106_CR28","doi-asserted-by":"crossref","unstructured":"Puri, R., Stok, L., & Bhattacharya, S. (2005). Keeping hot chips cool. In Design automation conference (DAC) (pp. 285\u2013 288).","DOI":"10.1145\/1065579.1065653"},{"key":"1106_CR29","unstructured":"Casale-Brunet, S., Bezati, E., Alberti, C., Mattavelli, M., Amaldi, E., & Janneck, J. (2013). Partitioning and optimization of high level stream applications for multi clock domain architectures. In IEEE Workshop on Signal Processing Systems (siPS) (pp. 177\u2013182)."},{"issue":"10","key":"1106_CR30","first-page":"1303","volume":"28","author":"R Ren","year":"2014","unstructured":"Ren, R., Wei, J., Mart\u00ednez, E.J., Gonz\u00e1lez, M.G., \u00c1lvaro, C.S., & del Oso, F.P. (2014). A PMC-driven methodology for energy estimation in RVC-CAL video codec specifications. Signal Processing: Image Communication, 28(10), 1303\u20131314.","journal-title":"Signal Processing: Image Communication"},{"key":"1106_CR31","first-page":"1","volume":"2012","author":"AG Schmidt","year":"2012","unstructured":"Schmidt, A.G., Steiner, N., French, M., & Sass, R. (2012). Hwpmi: an extensible performance monitoring infrastructure for improving hardware design and productivity on fpgas. International Journal of Reconfigurable Computing, 2012, 1\u201312.","journal-title":"International Journal of Reconfigurable Computing"},{"key":"1106_CR32","doi-asserted-by":"crossref","unstructured":"Lucarz, C., Roquier, G., & Mattavelli, M. (2010). High level design space exploration of RVC codec specifications for multi-core heterogeneous platforms. In Conference on design and architectures for signal and image processing (DASIP) (pp. 191\u2013198).","DOI":"10.1109\/DASIP.2010.5706264"},{"key":"1106_CR33","unstructured":"Rahman, A.A.A., Thavot, R., Casale-Brunet, S., Bezati, E., & Mattavelli, M. (2012). Design space exploration strategies for FPGA implementation of signal processing systems using CAL dataflow program. In Conference on design and architectures for signal and image processing (DASIP) (pp. 1\u20138)."},{"key":"1106_CR34","doi-asserted-by":"crossref","unstructured":"Meloni, P., Pomata, S., Tuveri, G., Secchi, S., Raffo, L., & Lindwer, M. (2012). Enabling fast ASIP design space exploration: an fpga-based runtime reconfigurable prototyper. VLSI Design.","DOI":"10.1155\/2012\/580584"},{"key":"1106_CR35","doi-asserted-by":"crossref","unstructured":"Palumbo, F., Sau, C., & Raffo, L. (2013). DSE And profiling of Multi-Context Coarse-Grained reconfigurable systems. In International symposium on image and signal processing and analysis (ISPA) (pp. 744\u2013749).","DOI":"10.1109\/ISPA.2013.6703836"},{"key":"1106_CR36","doi-asserted-by":"crossref","unstructured":"Zhang, Y., Roivainen, J., & Mammela, A. (2006). Clock-gating in FPGAs: a Novel and Comparative Evaluation. In EUROMICRO Conference on conference on digital system design: architectures, Methods and Tools (DSD) (pp. 584\u2013590).","DOI":"10.1109\/DSD.2006.32"},{"key":"1106_CR37","doi-asserted-by":"crossref","unstructured":"Bezati, E., Casale-Brunet, S., Mattavelli, M., & Janneck, J. W. (2014). Coarse grain clock gating of streaming applications in programmable logic implementations. In Proceedings of the 2014 electronic system level synthesis conference (ESLsyn) (pp. 1\u20136).","DOI":"10.1109\/ESLsyn.2014.6850387"},{"key":"1106_CR38","unstructured":"Silicon Integration Initiative (2014). Si2 Common Power Format SpecificationTM - Version 2.1."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-016-1106-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-016-1106-9\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-016-1106-9","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-016-1106-9.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,1]],"date-time":"2019-06-01T08:22:30Z","timestamp":1559377350000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-016-1106-9"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2,9]]},"references-count":38,"journal-issue":{"issue":"1","published-print":{"date-parts":[[2017,4]]}},"alternative-id":["1106"],"URL":"https:\/\/doi.org\/10.1007\/s11265-016-1106-9","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2016,2,9]]}}}