{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T00:06:50Z","timestamp":1775520410962,"version":"3.50.1"},"reference-count":24,"publisher":"Springer Science and Business Media LLC","issue":"3","license":[{"start":{"date-parts":[[2017,4,29]],"date-time":"2017-04-29T00:00:00Z","timestamp":1493424000000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["61401197"],"award-info":[{"award-number":["61401197"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100004608","name":"Natural Science Foundation of Jiangsu Province","doi-asserted-by":"publisher","award":["BK20151477"],"award-info":[{"award-number":["BK20151477"]}],"id":[{"id":"10.13039\/501100004608","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1007\/s11265-017-1249-3","type":"journal-article","created":{"date-parts":[[2017,4,29]],"date-time":"2017-04-29T15:45:36Z","timestamp":1493480736000},"page":"409-419","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":21,"title":["Design of High-Speed Wide-Word Hybrid Parallel-Prefix\/Carry-Select and Skip Adders"],"prefix":"10.1007","volume":"90","author":[{"given":"Xiaoping","family":"Cui","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8398-8648","authenticated-orcid":false,"given":"Weiqiang","family":"Liu","sequence":"additional","affiliation":[]},{"given":"Shumin","family":"Wang","sequence":"additional","affiliation":[]},{"suffix":"Jr","given":"Earl E.","family":"Swartzlander","sequence":"additional","affiliation":[]},{"given":"Fabrizio","family":"Lombardi","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2017,4,29]]},"reference":[{"issue":"8","key":"1249_CR1","doi-asserted-by":"publisher","first-page":"920","DOI":"10.1109\/12.156534","volume":"41","author":"P Chan","year":"1992","unstructured":"Chan, P., Schlag, M., Thomborson, C., & Oklobdzija, V. (1992). Delay optimization of carry-skip adders and block carry-lookahead adders using multidimensional dynamic programming. IEEE Transactions on Computers, 41(8), 920\u2013930.","journal-title":"IEEE Transactions on Computers"},{"key":"1249_CR2","doi-asserted-by":"crossref","unstructured":"Burgess, N. (2001). Accelerated carry-skip adders with low hardware cost. In Proceedings of the 35th Asilomar Conf. Signals, Systems and Computers (pp. 852\u2013856).","DOI":"10.1109\/ACSSC.2001.987044"},{"issue":"10","key":"1249_CR3","doi-asserted-by":"publisher","first-page":"689","DOI":"10.1109\/82.539001","volume":"43","author":"C Nagendra","year":"1996","unstructured":"Nagendra, C., Irwin, M., & Owens, R. (1996). Area-time-power tradeoffs in parallel adders. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 43(10), 689\u2013702.","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"3","key":"1249_CR4","doi-asserted-by":"publisher","first-page":"235","DOI":"10.1109\/TVLSI.2004.824305","volume":"12","author":"A Neve","year":"2004","unstructured":"Neve, A., Schettler, H., Ludwig, T., & Flandre, D. (2004). Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Transactions on VLSI Systems, 12(3), 235\u2013244.","journal-title":"IEEE Transactions on VLSI Systems"},{"issue":"22","key":"1249_CR5","doi-asserted-by":"publisher","first-page":"2101","DOI":"10.1049\/el:19981706","volume":"34","author":"T Chang","year":"1998","unstructured":"Chang, T., & Hsiao, M. (1998). Carry-select adder using single ripple carry adder. Electronics Letters, 34(22), 2101\u20132103.","journal-title":"Electronics Letters"},{"issue":"10","key":"1249_CR6","doi-asserted-by":"publisher","first-page":"614","DOI":"10.1049\/el:20010430","volume":"37","author":"Y Kim","year":"2001","unstructured":"Kim, Y., & Kim, L. (2001). 64-bit carry-select adder with reduced area. Electronics Letters, 37(10), 614\u2013615.","journal-title":"Electronics Letters"},{"key":"1249_CR7","unstructured":"He Y., Chang C. & Gu J. (2005) An area efficient 64-bit square root carry-select adder for low power applications. In Proceedings of the Int. Symp. Circuits and Syst. (pp. 4082\u20134085)."},{"issue":"3","key":"1249_CR8","doi-asserted-by":"publisher","first-page":"155","DOI":"10.1147\/rd.252.0156","volume":"25","author":"H Ling","year":"1981","unstructured":"Ling, H. (1981). High-speed binary adder. IBM Journal of Research and Development, 25(3), 155\u2013166.","journal-title":"IBM Journal of Research and Development"},{"issue":"3","key":"1249_CR9","doi-asserted-by":"publisher","first-page":"326","DOI":"10.1109\/TVLSI.2007.915507","volume":"16","author":"S Das","year":"2008","unstructured":"Das, S., & Khatri, S. (2008). A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic. IEEE Transactions on VLSI Systems, 16(3), 326\u2013331.","journal-title":"IEEE Transactions on VLSI Systems"},{"issue":"8","key":"1249_CR10","first-page":"831","volume":"C-22","author":"P Kogge","year":"1980","unstructured":"Kogge, P., & Stone, H. (1980). A parallel algorithm for the efficient solution of a general class of recurrence equations. IEEE Transactions on Computers, C-22(8), 831\u2013838.","journal-title":"IEEE Transactions on Computers"},{"issue":"3","key":"1249_CR11","doi-asserted-by":"publisher","first-page":"260","DOI":"10.1109\/TC.1982.1675982","volume":"C-31","author":"R Brent","year":"1982","unstructured":"Brent, R., & Kung, H. (1982). A regular layout for parallel adders. IEEE Transactions on Computers, C-31(3), 260\u2013264.","journal-title":"IEEE Transactions on Computers"},{"issue":"2","key":"1249_CR12","doi-asserted-by":"publisher","first-page":"226","DOI":"10.1109\/TEC.1960.5219822","volume":"EC-9","author":"J Sklansky","year":"1960","unstructured":"Sklansky, J. (1960). Conditional-sum addition logic. IRE Transactions on Electronic Computers, EC-9(2), 226\u2013231.","journal-title":"IRE Transactions on Electronic Computers"},{"issue":"4","key":"1249_CR13","doi-asserted-by":"publisher","first-page":"831","DOI":"10.1145\/322217.322232","volume":"27","author":"R Ladner","year":"1980","unstructured":"Ladner, R., & Fischer, M. (1980). Parallel prefix computation. Journal of the ACM, 27(4), 831\u2013838.","journal-title":"Journal of the ACM"},{"issue":"8","key":"1249_CR14","doi-asserted-by":"publisher","first-page":"931","DOI":"10.1109\/12.156535","volume":"41","author":"T Lynch","year":"1992","unstructured":"Lynch, T., & Swartzlander Jr., E. (1992). A spanning tree carry lookahead adder. IEEE Transactions on Computers, 41(8), 931\u2013939.","journal-title":"IEEE Transactions on Computers"},{"issue":"2","key":"1249_CR15","doi-asserted-by":"publisher","first-page":"225","DOI":"10.1109\/TC.2005.26","volume":"54","author":"G Dimitrakopoulos","year":"2005","unstructured":"Dimitrakopoulos, G., & Nikolos, D. (2005). High-speed parallel-prefix VLSI Ling adders. IEEE Transactions on Computers, 54(2), 225\u2013231.","journal-title":"IEEE Transactions on Computers"},{"key":"1249_CR16","unstructured":"Han T. & Carlson D. (1987). Fast area efficient VLSI adders. In Proceedings of the 8th Int. Symp. Computer Arithmetic (pp. 49\u201356)."},{"issue":"10","key":"1249_CR17","doi-asserted-by":"publisher","first-page":"1517","DOI":"10.1109\/TCAD.2014.2341926","volume":"33","author":"S Roy","year":"2014","unstructured":"Roy, S., Choudhury, M., Puriand, R., & Pan, D. (2014). Towards optimal performance-area trade-off in adders by synthesis of parallel prefix structures. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 33(10), 1517\u20131530.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"12","key":"1249_CR18","doi-asserted-by":"publisher","first-page":"1612","DOI":"10.1109\/12.214671","volume":"41","author":"N Quach","year":"1992","unstructured":"Quach, N., & Flynn, M. (1992). High speed addition in CMOS. IEEE Transactions on Computers, 41(12), 1612\u20131615.","journal-title":"IEEE Transactions on Computers"},{"issue":"1","key":"1249_CR19","doi-asserted-by":"publisher","first-page":"336","DOI":"10.1109\/TCSI.2007.913610","volume":"55","author":"Y He","year":"2008","unstructured":"He, Y., & Chang, C. (2008). A power-delay efficient hybrid carry-lookahead carry-select based redundant binary to two\u2019s complement converter. IEEE Transactions on Circuits and Systems I: Regular Papers, 55(1), 336\u2013346.","journal-title":"IEEE Transactions on Circuits and Systems I: Regular Papers"},{"issue":"2","key":"1249_CR20","doi-asserted-by":"publisher","first-page":"569","DOI":"10.1109\/JSSC.2008.2010795","volume":"44","author":"R Ziatanovici","year":"2009","unstructured":"Ziatanovici, R., Kao, S., & Nikolic, B. (2009). Energy-delay of optimization 64-bit carry-lookahead adders with a 240ps 90nm CMOS design example. IEEE Journal of Solid-State Circuits, 44(2), 569\u2013583.","journal-title":"IEEE Journal of Solid-State Circuits"},{"issue":"12","key":"1249_CR21","doi-asserted-by":"publisher","first-page":"1495","DOI":"10.1109\/12.260639","volume":"42","author":"V Kantabutra","year":"1993","unstructured":"Kantabutra, V. (1993). A recursive carry-lookahead\/carry-select hybrid adder. IEEE Transactions on Computers, 42(12), 1495\u20131499.","journal-title":"IEEE Transactions on Computers"},{"issue":"1","key":"1249_CR22","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/82.996053","volume":"49","author":"Y Wang","year":"2002","unstructured":"Wang, Y., Pai, C., & Song, X. (2002). The design of hybrid carry-lookahead\/carry-select adders. IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 49(1), 16\u201324.","journal-title":"IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing"},{"issue":"4","key":"1249_CR23","doi-asserted-by":"publisher","first-page":"1165","DOI":"10.1109\/TC.2015.2441711","volume":"65","author":"X Cui","year":"2016","unstructured":"Cui, X., Liu, W., Chen, X., Swartzlander Jr., E., & Lombardi, F. (2016). A modified partial product generator for redundant binary multipliers. IEEE Transactions on Computers, 65(4), 1165\u20131171.","journal-title":"IEEE Transactions on Computers"},{"key":"1249_CR24","unstructured":"Cui X., Liu W., Dong W. & Lombardi F. (2016). A Parallel Decimal Multiplier Using Hybrid BCD Codes. In Proceedings of the 23rd IEEE Symp. on Computer Arithmetic (pp. 150\u2013155)."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-017-1249-3\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-017-1249-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-017-1249-3.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,2,17]],"date-time":"2020-02-17T15:50:22Z","timestamp":1581954622000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-017-1249-3"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,4,29]]},"references-count":24,"journal-issue":{"issue":"3","published-print":{"date-parts":[[2018,3]]}},"alternative-id":["1249"],"URL":"https:\/\/doi.org\/10.1007\/s11265-017-1249-3","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2017,4,29]]},"assertion":[{"value":"26 February 2016","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 December 2016","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 April 2017","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"29 April 2017","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}