{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T14:38:01Z","timestamp":1740148681658,"version":"3.37.3"},"reference-count":44,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2017,9,27]],"date-time":"2017-09-27T00:00:00Z","timestamp":1506470400000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"name":"MediaTek Inc., Hsin-chu, Taiwan","award":["MOST 105-2622-8-002-002"],"award-info":[{"award-number":["MOST 105-2622-8-002-002"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1007\/s11265-017-1285-z","type":"journal-article","created":{"date-parts":[[2017,9,26]],"date-time":"2017-09-26T22:38:52Z","timestamp":1506465532000},"page":"247-259","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Rapid Hybrid Simulation Methods for Exploring the Design Space of Signal Processors with Dynamic and Scalable Timing Models"],"prefix":"10.1007","volume":"91","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9017-3778","authenticated-orcid":false,"given":"Chih-Wei","family":"Yeh","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chia-Heng","family":"Tu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Shih-Hao","family":"Hung","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2017,9,27]]},"reference":[{"key":"1285_CR1","unstructured":"Intel performance bottleneck (2012). Loads blocked by store forwarding \n                    https:\/\/software.intel.com\/en-us\/forums\/intel-performance-bottleneck-analyzer\/topic\/333586\n                    \n                  ."},{"key":"1285_CR2","unstructured":"Intel developer forum: 4k aliasing. \n                    https:\/\/software.intel.com\/en-us\/forums\/intel-vtune-amplifier-xe\/topic\/606846\n                    \n                   (2016)."},{"key":"1285_CR3","unstructured":"Intel performance bottleneck: 4k aliasing. \n                    https:\/\/software.intel.com\/en-us\/node\/544395\n                    \n                   (2016)."},{"key":"1285_CR4","unstructured":"Andersen, E. Buildroot: making embedded linux easy. \n                    https:\/\/buildroot.org\/\n                    \n                  ."},{"key":"1285_CR5","unstructured":"Angiolini, F., Ceng, J., Leupers, R., Ferrari, F., Ferri, C., & Benini, L. (2006). An integrated open framework for heterogeneous mpsoc design space exploration. In Proceedings of the conference on design, automation and test in Europe: proceedings (pp. 1145\u20131150.) European Design and Automation Association."},{"issue":"7","key":"1285_CR6","doi-asserted-by":"publisher","first-page":"1083","DOI":"10.1109\/TCAD.2010.2049053","volume":"29","author":"G Beltrame","year":"2010","unstructured":"Beltrame, G., Fossati, L., & Sciuto, D. (2010). Decision-theoretic design space exploration of multiprocessor platforms. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 29(7), 1083\u20131095.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"issue":"2","key":"1285_CR7","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., Beckmann, B., Black, G., Reinhardt, S. K., Saidi, A., Basu, A., Hestness, J., Hower, D. R., Krishna, T., Sardashti, S., & et al. (2011). The gem5 simulator. ACM SIGARCH Computer Architecture News, 39(2), 1\u20137.","journal-title":"ACM SIGARCH Computer Architecture News"},{"issue":"4","key":"1285_CR8","doi-asserted-by":"publisher","first-page":"52","DOI":"10.1109\/MM.2006.82","volume":"26","author":"NL Binkert","year":"2006","unstructured":"Binkert, N. L., Dreslinski, R. G., Hsu, L. R., Lim, K. T., Saidi, A. G., & Reinhardt, S. K. (2006). The m5 simulator: modeling networked systems. IEEE Micro, 26(4), 52\u201360.","journal-title":"IEEE Micro"},{"key":"1285_CR9","unstructured":"Bray, T. (2014). The javascript object notation (json) data interchange format. \n                    https:\/\/en.wikipedia.org\/wiki\/JSON\n                    \n                  ."},{"issue":"3","key":"1285_CR10","doi-asserted-by":"publisher","first-page":"13","DOI":"10.1145\/268806.268810","volume":"25","author":"D Burger","year":"1997","unstructured":"Burger, D., & Austin, T. M. (1997). The simplescalar tool set, version 2.0. ACM SIGARCH Computer Architecture News, 25(3), 13\u201325.","journal-title":"ACM SIGARCH Computer Architecture News"},{"key":"1285_CR11","unstructured":"Calborean, H., Jahr, R., Ungerer, T., & Vintan, L. (2011). Optimizing a superscalar system using multi-objective design space exploration. In Proceedings of the 18th international conference on control systems and computer science (CSCS), (Vol. 1, pp. 339\u2013346). Bucharest."},{"key":"1285_CR12","unstructured":"Calborean, H., & Vintan, L. (2010). An automatic design space exploration framework for multicore architecture optimizations. In 2010 9th on roedunet international conference (RoEduNet) (pp. 202\u2013207). New York: IEEE."},{"key":"1285_CR13","unstructured":"Chen, T., Guo, Q., Tang, K., Temam, O., Xu, Z., Zhou, Z. H., & Chen, Y. (2014). Archranker: a ranking approach to design space exploration. In 2014 ACM\/IEEE 41st International symposium on computer architecture (ISCA) (pp. 85\u201396). New York: IEEE."},{"key":"1285_CR14","unstructured":"Cheng, J. J., Hung, S. H., & Yeh, C. W. (2015). Rapid analysis of interprocessor communications on heterogeneous system architectures via parallel cache emulation. In Proceedings of the 2015 conference on research in adaptive and convergent systems (pp. 418\u2013423). New York: ACM."},{"key":"1285_CR15","unstructured":"Chiou, D., Sunwoo, D., Kim, J., Patil, N. A., Reinhart, W., Johnson, D. E., Keefe, J., & Angepat, H. (2007). Fpga-accelerated simulation technologies (fast): fast, full-system, cycle-accurate simulators. In Proceedings of the 40th Annual IEEE\/ACM international symposium on microarchitecture (pp. 249\u2013261). Washington, D.C.: IEEE Computer Society."},{"key":"1285_CR16","unstructured":"Ding, J. H., Hsu, W. C., Jeng, B. C., Hung, S. H., & Chung, Y. C. (2014). Hsaemu: a full system emulator for hsa platforms. In Proceedings of the 2014 international conference on hardware\/software codesign and system synthesis (p. 26). New York: ACM."},{"key":"1285_CR17","unstructured":"Dubach, C., Jones, T., & O\u2019Boyle, M. (2007). Microarchitectural design space exploration using an architecture-centric approach. In Proceedings of the 40th Annual IEEE\/ACM international symposium on microarchitecture (pp. 262\u2013271). Washington, D.C.: IEEE Computer Society."},{"key":"1285_CR18","unstructured":"Durillo, J. J., Nebro, A. J., & Alba, E. (2010). The jmetal framework for multi-objective optimization: design and architecture. In IEEE congress on evolutionary computation (pp. 1\u20138). New York: IEEE."},{"key":"1285_CR19","unstructured":"Dutta, R., Roy, J., & Vemuri, R. (1992). Distributed design-space exploration for high-level synthesis systems. In Proceedings of the 29th ACM\/IEEE design automation conference (pp. 644\u2013650). Washington, D.C.: IEEE Computer Society Press."},{"key":"1285_CR20","unstructured":"Edler, J., & Hill, M.D. (1998). Dinero iv trace-driven uniprocessor cache simulator."},{"key":"1285_CR21","unstructured":"Guthaus, M. R., Ringenberg, J. S., Ernst, D., Austin, T. M., Mudge, T., & Brown, R. B. (2001). Mibench: a free, commercially representative embedded benchmark suite. In 2001 IEEE International workshop on workload characterization, 2001. WWC-4 (pp. 3\u201314). New York: IEEE."},{"key":"1285_CR22","unstructured":"Hsu, H. C., Yeh, C. W., Hung, S. H., Hsu, W. C., King, C. T., & Chung, Y. C. (2016). Hsaemu 2.0: full system emulation for hsa platforms with soft-mmu. In Proceedings of the international conference on research in adaptive and convergent systems (pp. 230\u2013235). New York: ACM."},{"key":"1285_CR23","unstructured":"Hung, S. H., Chen, J. H., Tu, C. H., & Shieh, J. P. (2012). Adset: a framework of rapid design space exploration for android-based systems. In 2012 IEEE 1st Global conference on consumer electronics (GCCE) (pp. 586\u2013587). New York: IEEE."},{"key":"1285_CR24","unstructured":"Hung, S. H., Kuo, T. W., Shih, C. S., & Tu, C. H. (2012). System-wide profiling and optimization with virtual machines. In 2012 17th Asia and South Pacific design automation conference (ASP-DAC) (pp. 395\u2013400). New York: IEEE."},{"key":"1285_CR25","unstructured":"Hung, S. H., Liang, F. T., Tu, C. H., & Chang, N. (2013). Performance and power estimation for mobile-cloud applications on virtualized platforms. In 2013 Seventh international conference on innovative mobile and internet services in ubiquitous computing (IMIS) (pp. 260\u2013267). New York: IEEE."},{"issue":"4","key":"1285_CR26","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1328195.1328196","volume":"4","author":"E Ipek","year":"2008","unstructured":"Ipek, E., McKee, S. A., Singh, K., Caruana, R., Supinski, B.R.D., & Schulz, M. (2008). Efficient architectural design space exploration via predictive modeling. ACM Transactions on Architecture and Code Optimization (TACO), 4(4), 1.","journal-title":"ACM Transactions on Architecture and Code Optimization (TACO)"},{"key":"1285_CR27","volume-title":"Introduction to network simulator NS2","author":"T Issariyakul","year":"2011","unstructured":"Issariyakul, T., & Hossain, E. (2011). Introduction to network simulator NS2. Berlin: Springer Science & Business Media."},{"key":"1285_CR28","unstructured":"Kang, E., Jackson, E., & Schulte, W. (2010). An approach for effective design space exploration. In Modeling, development, and verification of adaptive systems foundations of computer software (pp. 33\u201354). Berlin: Springer."},{"key":"1285_CR29","doi-asserted-by":"publisher","unstructured":"Lin, C.Y., Chen, P.Y., Tseng, C.K., Huang, C.W., Weng, C.C., Kuan, C.B., Lin, S.H., Huang, S.Y., & Lee, J.K. (2010). Power aware sid-based simulator for embedded multicore dsp subsystems. In Proceedings of the eighth IEEE\/ACM\/IFIP international conference on hardware\/software codesign and system synthesis, CODES\/ISSS \u201910 (pp. 95\u2013104). New York: ACM, DOI \n                    https:\/\/doi.org\/10.1145\/1878961.1878981\n                    \n                  , (to appear in print).","DOI":"10.1145\/1878961.1878981"},{"key":"1285_CR30","unstructured":"Liu, H. Y., & Carloni, L. P. (2013). On learning-based methods for design-space exploration with high-level synthesis. In Proceedings of the 50th annual design automation conference (p. 50). New York: ACM."},{"key":"1285_CR31","unstructured":"Miettinen, A. P., Hirvisalo, V., & Knuuttila, J. (2011). Using qemu in timing estimation for mobile software development.In 1st international QEMU users\u2019 forum (Vol. 1, pp. 19\u201322)."},{"issue":"7","key":"1285_CR32","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1145\/566225.513835","volume":"37","author":"S Mohanty","year":"2002","unstructured":"Mohanty, S., Prasanna, V. K., Neema, S., & Davis, J. (2002). Rapid design space exploration of heterogeneous embedded systems using symbolic search and multi-granular simulation. ACM SIGPLAN Notices, 37 (7), 18\u201327.","journal-title":"ACM SIGPLAN Notices"},{"key":"1285_CR33","unstructured":"Ozisikyilmaz, B., Memik, G., & Choudhary, A. (2008). Efficient system design space exploration using machine learning techniques. In Proceedings of the 45th annual design automation conference (pp. 966\u2013969): ACM."},{"issue":"1","key":"1285_CR34","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1109\/LCA.2014.2299539","volume":"14","author":"J Power","year":"2015","unstructured":"Power, J., Hestness, J., Orr, M. S., Hill, M. D., & Wood, D.A. (2015). gem5-gpu: a heterogeneous cpu-gpu simulator. IEEE Computer Architecture Letters, 14(1), 34\u201336.","journal-title":"IEEE Computer Architecture Letters"},{"key":"1285_CR35","unstructured":"Pullini, A., Conti, F., Rossi, D., Loi, I., Gautschi, M., & Benini, L. (2016). A heterogeneous multi-core system-on-chip for energy efficient brain inspired vision. In 2016 IEEE International symposium on circuits and systems (ISCAS) (pp. 2910\u20132910). New York: IEEE."},{"key":"1285_CR36","unstructured":"Renau, J., Fraguela, B., Tuck, J., Liu, W., Prvulovic, M., Ceze, L., Sarangi, S., Sack, P., Strauss, K., & Montesinos, P. (2005). Sesc: cycle accurate architectural simulator. Retrieved November 19 2013."},{"issue":"1","key":"1285_CR37","doi-asserted-by":"publisher","first-page":"16","DOI":"10.1109\/L-CA.2011.4","volume":"10","author":"P Rosenfeld","year":"2011","unstructured":"Rosenfeld, P., Cooper-Balis, E., & Jacob, B. (2011). Dramsim2: a cycle accurate memory system simulator. IEEE Computer Architecture Letters, 10(1), 16\u201319.","journal-title":"IEEE Computer Architecture Letters"},{"key":"1285_CR38","unstructured":"Sanchez, D., & Kozyrakis, C. (2013). Zsim: fast and accurate microarchitectural simulation of thousand-core systems. In ACM SIGARCH Computer architecture news, (Vol. 41 pp. 475\u2013486): ACM."},{"key":"1285_CR39","unstructured":"Schatz, B., Holzl, F., & Lundkvist, T. (2010). Design-space exploration through constraint-based model-transformation. In 2010 17th IEEE International conference and workshops on engineering of computer based systems (ECBS) (pp. 173\u2013182). New York: IEEE."},{"key":"1285_CR40","unstructured":"Stoif, C., Schoeberl, M., Liccardi, B., & Haase, J. (2011). Hardware synchronization for embedded multi-core processors. In 2011 IEEE International symposium of circuits and systems (ISCAS) (pp. 2557\u20132560). New York: IEEE."},{"issue":"4","key":"1285_CR41","doi-asserted-by":"publisher","first-page":"36","DOI":"10.1145\/2348839.2348840","volume":"17","author":"C Tu","year":"2012","unstructured":"Tu, C., Hung, S., & Tsai, T. (2012). Mcemu: a framework for software development and performance analysis of multicore systems. ACM Transactions on Design Automation of Electronic Systems, 17(4), 36. \n                    https:\/\/doi.org\/10.1145\/2348839.2348840\n                    \n                  .","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"1285_CR42","unstructured":"Ubal, R., Sahuquillo, J., Petit, S., & L\u00f3pez, P. (2007). Multi2sim: a simulation framework to evaluate multicore-multithread processors. In IEEE 19th International symposium on computer architecture and high performance computing (pp. 62\u201368). New York: Citeseer."},{"key":"1285_CR43","unstructured":"Yourst, M. T. (2007). Ptlsim: a cycle accurate full system x86-64 microarchitectural simulator. In IEEE International symposium on performance analysis of systems & software, 2007. ISPASS 2007 (pp. 23\u201334). New York: IEEE."},{"key":"1285_CR44","unstructured":"Yu, K., Bi, J., & Tresp, V. (2006). Active learning via transductive experimental design. In Proceedings of the 23rd international conference on Machine learning (pp. 1081\u20131088). New York: ACM."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-017-1285-z\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-017-1285-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-017-1285-z.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,3,3]],"date-time":"2020-03-03T07:26:59Z","timestamp":1583220419000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-017-1285-z"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,9,27]]},"references-count":44,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2019,3]]}},"alternative-id":["1285"],"URL":"https:\/\/doi.org\/10.1007\/s11265-017-1285-z","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2017,9,27]]},"assertion":[{"value":"15 November 2016","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 May 2017","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"14 September 2017","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"27 September 2017","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}