{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T14:38:06Z","timestamp":1740148686998,"version":"3.37.3"},"reference-count":35,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T00:00:00Z","timestamp":1524700800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"funder":[{"DOI":"10.13039\/501100004370","name":"Tampere University of Technology","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100004370","id-type":"DOI","asserted-by":"crossref"}]},{"DOI":"10.13039\/501100002341","name":"Academy of Finland","doi-asserted-by":"crossref","award":["(project PLC)"],"award-info":[{"award-number":["(project PLC)"]}],"id":[{"id":"10.13039\/501100002341","id-type":"DOI","asserted-by":"crossref"}]},{"name":"Finnish Funding Agency","award":["1134\/31\/2015"],"award-info":[{"award-number":["1134\/31\/2015"]}]},{"name":"Artemis JU","award":["621439"],"award-info":[{"award-number":["621439"]}]}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1007\/s11265-018-1367-6","type":"journal-article","created":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T08:02:02Z","timestamp":1524729722000},"page":"1519-1532","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":0,"title":["Instruction Fetch Energy Reduction with Biased SRAMs"],"prefix":"10.1007","volume":"90","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4438-2031","authenticated-orcid":false,"given":"Joonas","family":"Multanen","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Timo","family":"Viitanen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Pekka","family":"J\u00e4\u00e4skel\u00e4inen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jarmo","family":"Takala","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,4,26]]},"reference":[{"issue":"15","key":"1367_CR1","doi-asserted-by":"publisher","first-page":"2787","DOI":"10.1016\/j.comnet.2010.05.010","volume":"54","author":"L Atzori","year":"2010","unstructured":"Atzori, L, Iera, A, Morabito, G. (2010). The internet of things: a survey. Computer Networks, 54(15), 2787\u20132805.","journal-title":"Computer Networks"},{"key":"1367_CR2","doi-asserted-by":"crossref","unstructured":"Taylor, M. (2012). Is dark silicon useful?: harnessing the four horsemen of the coming dark silicon apocalypse. In Proceedings of the 49th annual design automation conference.","DOI":"10.1145\/2228360.2228567"},{"issue":"1","key":"1367_CR3","doi-asserted-by":"publisher","first-page":"20","DOI":"10.1109\/JSSC.2012.2218067","volume":"48","author":"D Bol","year":"2013","unstructured":"Bol, D., De Vos, J., Hocquet, C., Botman, F., Durvaux, F., Boyd, S., Flandre, D., Legat, J. (2013). SleepWalker: a 25-MHz 0.4-V Sub-mm2 7- \u03bc\n                           m\n                           2 \u03bc W\/MHz microcontroller in 65-nm LP\/GP CMOS for low-carbon wireless sensor nodes. IEEE Journal of Solid-State Circuits, 48(1), 20\u201332.","journal-title":"IEEE Journal of Solid-State Circuits"},{"key":"1367_CR4","unstructured":"Carroll, A., & Heiser, G. (2010). An analysis of power consumption in a smartphone. In Proceedings of the USENIX annual technical conference. Boston."},{"issue":"1","key":"1367_CR5","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1109\/TCAD.2015.2481793","volume":"35","author":"X Fong","year":"2016","unstructured":"Fong, X., Kim, Y., Yogendra, K., Fan, D., Sengupta, A., Raghunathan, A., Roy, K. (2016). Spin-transfer torque devices for logic and memory: prospects and perspectives. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 35(1), 1\u201322.","journal-title":"IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"},{"key":"1367_CR6","unstructured":"Hu, J., Xue, C. J., Zhuge, Q., Tseng, W. C., Sha, E. H. -M. (2011). Towards energy efficient hybrid on-chip scratch pad memory with non-volatile memory. In Design, automation test in europe conference exhibition."},{"issue":"1","key":"1367_CR7","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1145\/605459.605461","volume":"2","author":"L Benini","year":"2003","unstructured":"Benini, L., Macii, A., Poncino, M. (2003). Energy-aware design of embedded memories: a survey of technologies, architectures, and optimization techniques. Transactions on Embedded Computing Systems, 2(1), 5\u201332.","journal-title":"Transactions on Embedded Computing Systems"},{"key":"1367_CR8","unstructured":"ISSCC. (2016). ISSCC 2016 tech trends. \n                    http:\/\/isscc.org\n                    \n                  ."},{"key":"1367_CR9","doi-asserted-by":"crossref","unstructured":"Azizi, N., & Najm, F. N. (2004). An asymmetric SRAM cell to lower gate leakage. In Proceedings of the 5th international symposium on quality electronic design. Hangzhou.","DOI":"10.1109\/ISQED.2004.1283728"},{"key":"1367_CR10","doi-asserted-by":"crossref","unstructured":"Imani, M., Patil, S., Rosing, T. S. (2015). Hierarchical design of robust and low data dependent FinFET based SRAM array. In Proceedings of the international symposium on nanoscale architectures. Boston.","DOI":"10.1109\/NANOARCH.2015.7180588"},{"key":"1367_CR11","doi-asserted-by":"crossref","unstructured":"Mori, H., Nakagawa, T., Kitahara, Y., Kawamoto, Y., Takagi, K., Yoshimoto, S., Izumi, S., Nii, K., Kawaguchi, H., Yoshimoto, M. (2015). A 298-fJ\/writecycle 650-fJ\/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. In Proceedings of the IEEE custom integrated circuits conference. San Jose.","DOI":"10.1109\/CICC.2015.7338360"},{"issue":"12","key":"1367_CR12","doi-asserted-by":"publisher","first-page":"873","DOI":"10.1109\/TCSII.2012.2231020","volume":"59","author":"A Teman","year":"2012","unstructured":"Teman, A., Mordakhay, A., Mezhibovsky, J., Fish, A. (2012). A 40-nm sub-threshold 5T SRAM bit cell with improved read and write stability. IEEE Transactions on Circuits and Systems II: Express Briefs, 59(12), 873\u2013877.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"issue":"2","key":"1367_CR13","doi-asserted-by":"publisher","first-page":"399","DOI":"10.1109\/16.19942","volume":"36","author":"KK Young","year":"1989","unstructured":"Young, K. K. (1989). Short-channel effect in fully depleted soi mosfets. IEEE Transactions on Electron Devices, 36(2), 399\u2013402.","journal-title":"IEEE Transactions on Electron Devices"},{"key":"1367_CR14","doi-asserted-by":"crossref","unstructured":"Multanen, J., Viitanen, T., J\u00e4\u00e4skel\u00e4inen, P., Takala, J. (2016). Xor-masking: a novel statistical method for instruction read energy reduction in contemporary SRAM technologies. In International workshop on signal processing systems. Dallas.","DOI":"10.1109\/SiPS.2016.19"},{"issue":"1","key":"1367_CR15","doi-asserted-by":"publisher","first-page":"49","DOI":"10.1109\/92.365453","volume":"3","author":"MR Stan","year":"1995","unstructured":"Stan, M. R., & Burleson, W. P. (1995). Bus-invert coding for low-power I\/O. IEEE Transactions on Very Large Scale Integration Systems, 3(1), 49\u201358.","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"issue":"2","key":"1367_CR16","doi-asserted-by":"publisher","first-page":"377","DOI":"10.1109\/92.924059","volume":"9","author":"Y Shin","year":"2001","unstructured":"Shin, Y., Chae, S. -I., Choi, K. (2001). Partial bus-invert coding for power optimization of application-specific systems. IEEE Transactions on Very Large Scale Integration Systems, 9(2), 377\u2013383.","journal-title":"IEEE Transactions on Very Large Scale Integration Systems"},{"key":"1367_CR17","unstructured":"Ji, G., & Hui, G. (2009). A segmental bus-invert coding method for instruction memory data bus power efficiency. In Proceedings of the IEEE international symposium on circuits and systems. Taipei."},{"issue":"1","key":"1367_CR18","doi-asserted-by":"publisher","first-page":"18","DOI":"10.1109\/MDT.2003.1173049","volume":"20","author":"P Petrov","year":"2003","unstructured":"Petrov, P., & Orailoglu, A. (2003). Application-specific instruction memory customizations for power-efficient embedded processors. IEEE Design Test of Computers, 20(1), 18\u201325.","journal-title":"IEEE Design Test of Computers"},{"issue":"4","key":"1367_CR19","doi-asserted-by":"publisher","first-page":"24","DOI":"10.1109\/54.329448","volume":"11","author":"C Su","year":"1994","unstructured":"Su, C., Tsui, C., Despain, A. (1994). Saving power in the control path of embedded processors. IEEE Design and Test of Computers, 11(4), 24\u201331.","journal-title":"IEEE Design and Test of Computers"},{"issue":"4","key":"1367_CR20","doi-asserted-by":"publisher","first-page":"568","DOI":"10.1109\/92.736129","volume":"6","author":"E. Musoll","year":"1998","unstructured":"Musoll, E., Lang, T., Cortadella, J. (1998). Working-zone encoding for reducing the energy in microprocessor address buses. IEEE Transactions on Very Large Scale Integration Systems, 6(4).","journal-title":"IEEE Transactions on Very Large Scale Integration (VLSI) Systems"},{"key":"1367_CR21","doi-asserted-by":"crossref","unstructured":"Benini, L., De Micheli, G., Macii, E., Poncino, M., Quez, S. (1997). System-level power optimization of special purpose applications: the beach solution. In Proceedings of the international symposium on low power electronics and design. Monterey.","DOI":"10.1145\/263272.263277"},{"issue":"3","key":"1367_CR22","doi-asserted-by":"publisher","first-page":"354","DOI":"10.1145\/1013948.1013953","volume":"9","author":"J Yang","year":"2004","unstructured":"Yang, J., Gupta, R., Zhang, C. (2004). Frequent value encoding for low power data buses. ACM Transactions on Design Automation of Electronic Systems, 9(3), 354\u2013384.","journal-title":"ACM Transactions on Design Automation of Electronic Systems"},{"key":"1367_CR23","volume-title":"Computer architecture: a quantitative approach","author":"J Hennessy","year":"2002","unstructured":"Hennessy, J., & Patterson, D. (2002). Computer architecture: a quantitative approach, 3rd edn. San Francisco: Morgan Kaufmann Publishers Inc.,.","edition":"3rd edn."},{"key":"1367_CR24","doi-asserted-by":"crossref","unstructured":"Parhami, B. (1991). Design of m-out-of-n bit-voters. In Conference record of the twenty-fifth asilomar conference on signals, systems and computers (Vol. 2). Pacific Grove.","DOI":"10.1109\/ACSSC.1991.186650"},{"issue":"7","key":"1367_CR25","doi-asserted-by":"publisher","first-page":"189","DOI":"10.1145\/780731.780759","volume":"38","author":"DC Suresh","year":"2003","unstructured":"Suresh, D. C., Najjar, W. A., Vahid, F., Villarreal, J. R., Stitt, G. (2003). Profiling tools for hardware\/software partitioning of embedded applications. SIGPLAN Notices, 38(7), 189\u2013198.","journal-title":"SIGPLAN Notices"},{"key":"1367_CR26","unstructured":"Lattice Semiconductor. Latticemico32 (2016). \n                    http:\/\/www.latticesemi.com\/en\/Products\/DesignSoftwareAndIP\/IntellectualProperty\/IPCore\/IPCores02\/LatticeMico32.aspx\n                    \n                  ."},{"key":"1367_CR27","doi-asserted-by":"crossref","unstructured":"Ben Salem, Z., Youssef, M. W., Abid, M. (2010). Prototyping cost-effective secure application server on a chip (sasoc) a case study for monitoring sensor network. In International conference on wireless and ubiquitous systems Sousse.","DOI":"10.1109\/ICWUS.2010.5670425"},{"key":"1367_CR28","doi-asserted-by":"publisher","first-page":"111","DOI":"10.1007\/978-3-642-28293-5_10","volume-title":"Architecture of Computing Systems \u2013 ARCS 2012","author":"Pascal Schleuniger","year":"2012","unstructured":"Schleuniger, P., McKee, S., Karlsson, S. (2012). Design principles for synthesizable processor cores."},{"key":"1367_CR29","doi-asserted-by":"crossref","unstructured":"Multanen, J., Kultala, H., Koskela, M., Viitanen, T., J\u00e4\u00e4skel\u00e4inen, P., Takala, J., Danielyan, A., Cruz, C. (2016). Opencl programmable exposed datapath high performance low-power image signal processor. In IEEE Nordic circuits and systems conference.","DOI":"10.1109\/NORCHIP.2016.7792906"},{"key":"1367_CR30","doi-asserted-by":"crossref","unstructured":"Esko, O., J\u00e4\u00e4skel\u00e4inen, P., Huerta, P., de La Lama, C. S., Takala, J., Martinez, J. I. (2010). Customized exposed datapath soft-core design flow with compiler support. In Proceedings of international conference on field programmable logic and applications. Washington, DC.","DOI":"10.1109\/FPL.2010.51"},{"key":"1367_CR31","doi-asserted-by":"crossref","unstructured":"Siti, M., & Fitz, M. P. (2006). A novel soft-output layered orthogonal lattice detector for multiple antenna communications. In International conference on communications (Vol. 4). Istanbul.","DOI":"10.1109\/ICC.2006.254962"},{"key":"1367_CR32","doi-asserted-by":"publisher","first-page":"242","DOI":"10.2197\/ipsjjip.17.242","volume":"17","author":"Yuko Hara","year":"2009","unstructured":"Hara, Y., Tomiyama, H., Honda, S., Takada, H. (2009). Proposal and quantitative analysis of the CHStone benchmark program suite for practical C-based high-level synthesis. Journal of Information Processing, 17, 242\u2013254.","journal-title":"Journal of Information Processing"},{"key":"1367_CR33","unstructured":"Zivojnovic, V., Martinez, J., Schlger, C., Meyr, H. (1994). DSPstone: a DSP-oriented benchmarking methodology. In Proceedings of the international conference on signal processing applications and technology. Dallas."},{"key":"1367_CR34","unstructured":"EEMBC \u2013. (2016). The embedded microprocessor benchmark consortium. Coremark benchmark. \n                    http:\/\/www.eembc.org\/coremark\n                    \n                  ."},{"issue":"3","key":"1367_CR35","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1347375.1347389","volume":"7","author":"R Wilhelm","year":"2008","unstructured":"Wilhelm, R, Engblom, J, Ermedahl, A, Holsti, N, Thesing, S, Whalley, D, Bernat, G, Ferdinand, C, Heckmann, R, Mitra, T, Mueller, F, Puaut, I, Puschner, P, Staschulat, J, Stenstr\u00f6m, P. (2008). The worst-case execution-time problem - overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems, 7(3), 1\u201353.","journal-title":"ACM Transactions on Embedded Computing Systems"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-018-1367-6\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1367-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1367-6.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,5,19]],"date-time":"2020-05-19T10:42:46Z","timestamp":1589884966000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-018-1367-6"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,26]]},"references-count":35,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2018,11]]}},"alternative-id":["1367"],"URL":"https:\/\/doi.org\/10.1007\/s11265-018-1367-6","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2018,4,26]]},"assertion":[{"value":"13 January 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"17 October 2017","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 April 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 April 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}