{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,5]],"date-time":"2026-03-05T15:33:44Z","timestamp":1772724824349,"version":"3.50.1"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"3-4","license":[{"start":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T00:00:00Z","timestamp":1524700800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1007\/s11265-018-1369-4","type":"journal-article","created":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T14:26:53Z","timestamp":1524752813000},"page":"379-397","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":2,"title":["Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit"],"prefix":"10.1007","volume":"91","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9842-8715","authenticated-orcid":false,"given":"Mehdi","family":"Alipour","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Trevor E.","family":"Carlson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"David","family":"Black-Schaffer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefanos","family":"Kaxiras","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,4,26]]},"reference":[{"key":"1369_CR1","doi-asserted-by":"crossref","unstructured":"Afram, F., Zeng, H., Ghose, K. (2013). A group-commit mechanism for ROB-based processors implementing the x86 ISA. In HPCA (pp. 47\u201358).","DOI":"10.1109\/HPCA.2013.6522306"},{"key":"1369_CR2","doi-asserted-by":"crossref","unstructured":"Alipour, M., Carlson, T.E., Kaxiras, S. (2017). Exploring the performance limits of out-of-order commit. In CF (pp. 211\u2013 220).","DOI":"10.1145\/3075564.3075581"},{"issue":"1","key":"1369_CR3","doi-asserted-by":"publisher","first-page":"42","DOI":"10.1109\/2.976918","volume":"35","author":"A Allan","year":"2002","unstructured":"Allan, A., Edenfeld, D., Joyner Jr. W.H., Kahng, A.B., Rodgers, M., Zorian, Y. (2002). 2001 technology roadmap for semiconductors. Computer, 35(1), 42\u201353.","journal-title":"Computer"},{"key":"1369_CR4","unstructured":"Badalone, R. (2015). Dram\u2019s surprising role in the cost of data centers. http:\/\/www.datacenterknowledge.com\/archives\/2015\/11\/12\/dont\/ ."},{"key":"1369_CR5","doi-asserted-by":"crossref","unstructured":"Bell, G.B., & Lipasti, M.H. (2004). Deconstructing commit. In ISPASS (pp. 68\u201377).","DOI":"10.1109\/ISPASS.2004.1291357"},{"issue":"2","key":"1369_CR6","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/2024716.2024718","volume":"39","author":"N Binkert","year":"2011","unstructured":"Binkert, N., Beckmann, B., Black, G., Reinhardt, S.K., Saidi, A., Basu, A., Hestness, J., Hower, D.R., Krishna, T., Sardashti, S., Sen, R., Sewell, K., Shoaib, M., Vaish, N., Hill, M.D., Wood, D.A. (2011). The gem5 simulator. SIGARCH Computer Architecture News, 39(2), 1\u20137.","journal-title":"SIGARCH Computer Architecture News"},{"key":"1369_CR7","doi-asserted-by":"crossref","unstructured":"Carlson, T.E., Heirman, W., Allam, O., Kaxiras, S., Eeckhout, L. (2015). The load slice core microarchitecture. In ISCA (pp. 272\u2013284).","DOI":"10.1145\/2749469.2750407"},{"key":"1369_CR8","doi-asserted-by":"crossref","unstructured":"Chou, Y., Fahs, B., Abraham, S. (2004). Microarchitecture optimizations for exploiting memory-level parallelism. In ISCA (pp. 76\u201388).","DOI":"10.1145\/1028176.1006708"},{"key":"1369_CR9","unstructured":"Corporation, I. (2016). Intel\u00ae 64 and ia-32 architectures optimization reference manual. http:\/\/www.intel.com\/content\/www\/us\/en\/architecture-and-technology\/64-ia-32-architectures-optimization-manual.html ."},{"key":"1369_CR10","unstructured":"Corporation, I. (2016). Intel\u00ae intel\u2019s \u2018tick-tock\u2019 seemingly dead, becomes \u2018process-architecture-optimization\u2019. http:\/\/www.anandtech.com\/show\/10183\/intels-tick-tock-seemingly-dead-becomes-process-architecture-optimization ."},{"key":"1369_CR11","unstructured":"Cristal, A., Ortega, D., Llosa, J., Valero, M. (2004). Outof- order commit processors. In HPCA (pp. 48\u201359)."},{"issue":"4","key":"1369_CR12","doi-asserted-by":"publisher","first-page":"389","DOI":"10.1145\/1044823.1044825","volume":"1","author":"A Cristal","year":"2004","unstructured":"Cristal, A., Santana, O.J., Valero, M., Mart\u00ednez, J.F. (2004). Toward kilo-instruction processors. ACM Transactions on Architecture and Code Optimization, 1(4), 389\u2013417.","journal-title":"ACM Transactions on Architecture and Code Optimization"},{"issue":"1","key":"1369_CR13","doi-asserted-by":"publisher","first-page":"21","DOI":"10.1109\/L-CA.2012.8","volume":"12","author":"N Duong","year":"2013","unstructured":"Duong, N., & Veidenbaum, A.V. (2013). Compiler-assisted, selective out-of-order commit. IEEE Computer Architecture Letters, 12(1), 21\u201324.","journal-title":"IEEE Computer Architecture Letters"},{"issue":"12","key":"1369_CR14","first-page":"249","volume":"8","author":"L Gwennap","year":"1994","unstructured":"Gwennap, L. (1994). Digital leads the pack with 21164. Microprocessor Report, 8(12), 249\u2013260.","journal-title":"Microprocessor Report"},{"key":"1369_CR15","doi-asserted-by":"crossref","unstructured":"Ham, T., Arag\u00f3n, J.L., Martonosi, M. (2015). Desc: decoupled supply-compute communication management for heterogeneous architectures. In MICRO (pp. 191\u2013203).","DOI":"10.1145\/2830772.2830800"},{"issue":"4","key":"1369_CR16","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1145\/1186736.1186737","volume":"34","author":"JL Henning","year":"2006","unstructured":"Henning, J.L. (2006). SPEC CPU2006 benchmark descriptions. SIGARCH Computer Architecture News, 34 (4), 1\u201317.","journal-title":"SIGARCH Computer Architecture News"},{"key":"1369_CR17","doi-asserted-by":"crossref","unstructured":"Hilton, A., & Roth, A. (2010). BOLT: energy-efficient out-of-order latency-tolerant execution. In HPCA (pp. 1\u201312).","DOI":"10.1109\/HPCA.2010.5416634"},{"key":"1369_CR18","unstructured":"Jaleel, A. (2010). Memory characterization of workloads using instrumentation driven simulation. http:\/\/www.glue.umd.edu\/ajaleel\/workload ."},{"key":"1369_CR19","unstructured":"Kroft, D. (1981). Lockup-free instruction fetch\/prefetch cache organization. In ISCA (pp. 81\u201387)."},{"key":"1369_CR20","doi-asserted-by":"crossref","unstructured":"Lee, D., Kim, Y., Seshadri, V., Liu, J., Subramanian, L., Mutlu, O. (2013). Tiered-latency dram: a low latency and low cost dram architecture. In HPCA (pp. 615\u2013626).","DOI":"10.1109\/HPCA.2013.6522354"},{"issue":"12","key":"1369_CR21","doi-asserted-by":"publisher","first-page":"1626","DOI":"10.1109\/TC.2009.95","volume":"58","author":"S Marti","year":"2009","unstructured":"Marti, S., Borras, J., Rodriguez, P., Tena, R., Marin, J. (2009). A complexity-effective out-of-order retirement microarchitecture. IEEE Transactions on Computers, 58(12), 1626\u2013 1639.","journal-title":"IEEE Transactions on Computers"},{"key":"1369_CR22","doi-asserted-by":"crossref","unstructured":"Martinez, J.F., Renau, J., Huang, M.C., Prvulovic, M. (2002). Cherry: checkpointed early resource recycling in out-of-order microprocessors. In MICRO (pp. 3\u201314).","DOI":"10.1109\/MICRO.2002.1176234"},{"issue":"10","key":"1369_CR23","doi-asserted-by":"publisher","first-page":"1244","DOI":"10.1109\/TC.2004.79","volume":"53","author":"T Monreal","year":"2004","unstructured":"Monreal, T., Vinals, V., Gonzalez, J., Gonzalez, A., Valero, M. (2004). Late allocation and early release of physical registers. IEEE Transactions on Computers, 53(10), 1244\u20131259.","journal-title":"IEEE Transactions on Computers"},{"key":"1369_CR24","doi-asserted-by":"crossref","unstructured":"Ros, A., Carlson, T.E., Alipour, M., Kaxiras, S. (2017). Non-speculative load-load reordering in TSO. In ISCA (pp. 187\u2013200).","DOI":"10.1145\/3079856.3080220"},{"issue":"5","key":"1369_CR25","doi-asserted-by":"publisher","first-page":"562","DOI":"10.1109\/12.4607","volume":"37","author":"JE Smith","year":"1988","unstructured":"Smith, J.E., & Pleszkun, A.R. (1988). Implementing precise interrupts in pipelined processors. IEEE Transactions on Computers, 37(5), 562\u2013573.","journal-title":"IEEE Transactions on Computers"},{"key":"1369_CR26","doi-asserted-by":"crossref","unstructured":"Sohi, G.S., & Vajapeyam, S. (1987). Instruction issue logic for high-performance, interruptable pipelined processors. In ISCA (pp. 27\u201334).","DOI":"10.1145\/30350.30354"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-018-1369-4\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1369-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1369-4.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T23:23:37Z","timestamp":1751585017000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-018-1369-4"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,4,26]]},"references-count":26,"journal-issue":{"issue":"3-4","published-print":{"date-parts":[[2019,3]]}},"alternative-id":["1369"],"URL":"https:\/\/doi.org\/10.1007\/s11265-018-1369-4","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,4,26]]},"assertion":[{"value":"10 August 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"11 March 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"16 April 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"26 April 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}