{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,27]],"date-time":"2026-03-27T17:13:02Z","timestamp":1774631582245,"version":"3.50.1"},"reference-count":26,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2018,5,1]],"date-time":"2018-05-01T00:00:00Z","timestamp":1525132800000},"content-version":"tdm","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1007\/s11265-018-1370-y","type":"journal-article","created":{"date-parts":[[2018,5,1]],"date-time":"2018-05-01T10:33:25Z","timestamp":1525170805000},"page":"1583-1592","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":19,"title":["SFF\u2014The Single-Stream FPGA-Optimized Feedforward FFT Hardware Architecture"],"prefix":"10.1007","volume":"90","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-9902-8825","authenticated-orcid":false,"given":"Carl","family":"Ingemarsson","sequence":"first","affiliation":[]},{"given":"Oscar","family":"Gustafsson","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,5,1]]},"reference":[{"key":"1370_CR1","doi-asserted-by":"publisher","unstructured":"Abdullah, S.S., Nam, H., McDermot, M., Abraham, J.A. (2009). A high throughput FFT processor with no multipliers. In Proceedings of the IEEE international conference on computer design. \n                    https:\/\/doi.org\/10.1109\/ICCD.2009.5413113\n                    \n                   (pp. 485\u2013490). Lake Tahoe.","DOI":"10.1109\/ICCD.2009.5413113"},{"issue":"12","key":"1370_CR2","doi-asserted-by":"publisher","first-page":"1982","DOI":"10.1109\/29.45545","volume":"37","author":"G Bi","year":"1989","unstructured":"Bi, G., & Jones, E.V. (1989). A pipelined FFT processor for word-sequential data. IEEE Transactions on Acoustics, Speech, and Signal Processing, 37(12), 1982\u20131985. \n                    https:\/\/doi.org\/10.1109\/29.45545\n                    \n                  .","journal-title":"IEEE Transactions on Acoustics, Speech, and Signal Processing"},{"issue":"12","key":"1370_CR3","doi-asserted-by":"publisher","first-page":"1234","DOI":"10.1109\/TCSII.2008.2008074","volume":"55","author":"YN Chang","year":"2008","unstructured":"Chang, Y.N. (2008). An efficient VLSI architecture for normal I\/O order pipeline FFT design. IEEE Transactions on Circuits and Systems II, 55(12), 1234\u20131238. \n                    https:\/\/doi.org\/10.1109\/TCSII.2008.2008074\n                    \n                  .","journal-title":"IEEE Transactions on Circuits and Systems II"},{"issue":"7","key":"1370_CR4","doi-asserted-by":"publisher","first-page":"2824","DOI":"10.1109\/TSP.2009.2016276","volume":"57","author":"A Cortes","year":"2009","unstructured":"Cortes, A., Velez, I., Sevillano, J.F. (2009). Radix FFTs: matricial representation and SDC\/SDF pipeline implementation. IEEE Transactions on Signal Processing, 57(7), 2824\u20132839. \n                    https:\/\/doi.org\/10.1109\/TSP.2009.2016276\n                    \n                  .","journal-title":"IEEE Transactions on Signal Processing"},{"key":"1370_CR5","doi-asserted-by":"publisher","unstructured":"Derafshi, Z.H., Frounchi, J., Taghipour, H. (2010). A high speed FPGA implementation of a 1024-point complex FFT processor. In International conference on computer network technology. \n                    https:\/\/doi.org\/10.1109\/ICCNT.2010.12\n                    \n                   (pp. 312\u2013315). Bangkok.","DOI":"10.1109\/ICCNT.2010.12"},{"issue":"10","key":"1370_CR6","doi-asserted-by":"publisher","first-page":"993","DOI":"10.1109\/T-C.1974.223800","volume":"C-23","author":"AM Despain","year":"1974","unstructured":"Despain, A.M. (1974). Fourier transform computers using CORDIC iterations. IEEE Transactions on Computers, C-23(10), 993\u20131001. \n                    https:\/\/doi.org\/10.1109\/T-C.1974.223800\n                    \n                  .","journal-title":"IEEE Transactions on Computers"},{"key":"1370_CR7","doi-asserted-by":"publisher","unstructured":"Ehliar, A. (2010). Optimizing Xilinx designs through primitive instantiation: guidelines, techniques, and tips. In Proceedings of the FPGAworld conference. \n                    https:\/\/doi.org\/10.1145\/1975482.1975484\n                    \n                   (pp. 20\u201327).","DOI":"10.1145\/1975482.1975484"},{"key":"1370_CR8","doi-asserted-by":"publisher","unstructured":"Ehliar, A., & Liu, D. (2009). An ASIC perspective on FPGA optimizations. In Proceedings of the international conference on field-programmable logic and applications. \n                    https:\/\/doi.org\/10.1109\/FPL.2009.5272311\n                    \n                   (pp. 218\u2013223).","DOI":"10.1109\/FPL.2009.5272311"},{"issue":"10","key":"1370_CR9","doi-asserted-by":"publisher","first-page":"1737","DOI":"10.1109\/TCSI.2016.2587822","volume":"63","author":"M Garrido","year":"2016","unstructured":"Garrido, M. (2016). A new representation of FFT algorithms using triangular matrices. IEEE Transactions on Circuits and Systems I, 63(10), 1737\u20131745. \n                    https:\/\/doi.org\/10.1109\/TCSI.2016.2587822\n                    \n                  .","journal-title":"IEEE Transactions on Circuits and Systems I"},{"issue":"10","key":"1370_CR10","doi-asserted-by":"publisher","first-page":"974","DOI":"10.1109\/TCSII.2016.2538119","volume":"63","author":"M Garrido","year":"2016","unstructured":"Garrido, M., Huang, S.J., Chen, S.G., Gustafsson, O. (2016). The serial commutator FFT. IEEE Transactions on Circuits and Systems II, 63(10), 974\u2013978. \n                    https:\/\/doi.org\/10.1109\/TCSII.2016.2538119\n                    \n                  .","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"1370_CR11","unstructured":"Garrido, M., Qureshi, F., Takala, J., Gustafsson, O. (2018). Hard- ware architectures for the fast Fourier transform. In Bhattacharyya, S.S., Deprettere, E.F., Leupers, R., Takala, J. (Eds.) Handbook of signal processing systems, 3rd edn: Springer."},{"issue":"1","key":"1370_CR12","doi-asserted-by":"publisher","first-page":"5","DOI":"10.1109\/TAU.1973.1162428","volume":"21","author":"B Gold","year":"1973","unstructured":"Gold, B., & Bially, T. (1973). Parallelism in fast Fourier transform hardware. IEEE Transactions on Audio and Electroacoustics, 21(1), 5\u201316. \n                    https:\/\/doi.org\/10.1109\/TAU.1973.1162428\n                    \n                  .","journal-title":"IEEE Transactions on Audio and Electroacoustics"},{"issue":"11","key":"1370_CR13","doi-asserted-by":"publisher","first-page":"1015","DOI":"10.1109\/T-C.1970.222826","volume":"C-19","author":"HL Groginsky","year":"1970","unstructured":"Groginsky, H.L., & Works, G.A. (1970). A pipeline fast Fourier transform. IEEE Transactions on Computers, C-19(11), 1015\u20131019. \n                    https:\/\/doi.org\/10.1109\/T-C.1970.222826\n                    \n                  .","journal-title":"IEEE Transactions on Computers"},{"key":"1370_CR14","doi-asserted-by":"publisher","unstructured":"He, S., & Torkelson, M. (1996). A new approach to pipeline FFT processor. In Proceedings of the international parallel processing symposium. \n                    https:\/\/doi.org\/10.1109\/IPPS.1996.508145\n                    \n                   (pp. 766\u2013770).","DOI":"10.1109\/IPPS.1996.508145"},{"key":"1370_CR15","doi-asserted-by":"publisher","unstructured":"Ingemarsson, C., K\u00e4llstr\u00f6m, P., Gustafsson, O. (2012). Using DSP block pre-adders in pipeline SDF FFT implementations in contemporary FPGAs. In Proceedings of the international conference on field-programmable logic and applications. \n                    https:\/\/doi.org\/10.1109\/FPL.2012.6339243\n                    \n                   (pp. 71\u201374).","DOI":"10.1109\/FPL.2012.6339243"},{"issue":"9","key":"1370_CR16","doi-asserted-by":"publisher","first-page":"2486","DOI":"10.1109\/TVLSI.2017.2710479","volume":"25","author":"C Ingemarsson","year":"2017","unstructured":"Ingemarsson, C., K\u00e4llstr\u00f6m, P., Qureshi, F., Gustafsson, O. (2017). Efficient FPGA mapping of pipeline SDF FFT cores. IEEE Transactions on VLSI Systems, 25(9), 2486\u20132497. \n                    https:\/\/doi.org\/10.1109\/TVLSI.2017.2710479\n                    \n                  .","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"1370_CR17","doi-asserted-by":"publisher","unstructured":"Li, J., Liu, F., Long, T., Mao, E. (2009). Research on pipeline R22SDF FFT. In Proceedings of the IET international radar conference. \n                    https:\/\/doi.org\/10.1049\/CP.2009.0174\n                    \n                   (pp. 1\u20135).","DOI":"10.1049\/CP.2009.0174"},{"issue":"1","key":"1370_CR18","doi-asserted-by":"publisher","first-page":"76","DOI":"10.1631\/jzus.C1000234","volume":"12","author":"X Liu","year":"2011","unstructured":"Liu, X., Yu, F., Wang, Z. (2011). A pipelined architecture for normal I\/O order FFT. Journal of Zhejiang University-Science C, 12(1), 76\u201382. \n                    https:\/\/doi.org\/10.1631\/JZUS.C1000234\n                    \n                  .","journal-title":"Journal of Zhejiang University-Science C"},{"issue":"4","key":"1370_CR19","doi-asserted-by":"publisher","first-page":"323","DOI":"10.1631\/jzus.C1000258","volume":"12","author":"Z Ma","year":"2011","unstructured":"Ma, Z., Yu, F., Ge, R., Wang, Z. (2011). An efficient radix-2 fast Fourier transform processor with ganged butterfly engines on field programmable gate arrays. Journal of Zhejiang University-Science C, 12(4), 323\u2013329. \n                    https:\/\/doi.org\/10.1631\/JZUS.C1000258\n                    \n                  .","journal-title":"Journal of Zhejiang University-Science C"},{"key":"1370_CR20","doi-asserted-by":"crossref","unstructured":"Qureshi, F., & Gustafsson, O. (2011). Generation of all radix-2 fast Fourier transform algorithms using binary trees. In Proceedings of the European conference on circuit theory and design (pp. 677\u2013680).","DOI":"10.1109\/ECCTD.2011.6043634"},{"issue":"5","key":"1370_CR21","doi-asserted-by":"publisher","first-page":"973","DOI":"10.1109\/TVLSI.2014.2319335","volume":"23","author":"Z Wang","year":"2015","unstructured":"Wang, Z., Liu, X., He, B., Yu, F. (2015). A combined SDC-SDF architecture for normal I\/O pipelined radix-2 FFT. IEEE Transactions on VLSI Systems, 23(5), 973\u2013977. \n                    https:\/\/doi.org\/10.1109\/TVLSI.2014.2319335\n                    \n                  .","journal-title":"IEEE Transactions on VLSI Systems"},{"key":"1370_CR22","doi-asserted-by":"publisher","DOI":"10.1016\/B978-012734530-7\/50001-5","volume-title":"DSP integrated circuits","author":"L Wanhammar","year":"1999","unstructured":"Wanhammar, L. (1999). DSP integrated circuits. New York: Academic."},{"issue":"5","key":"1370_CR23","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1109\/TC.1984.1676458","volume":"C-33","author":"EH Wold","year":"1984","unstructured":"Wold, E.H., & Despain, A.M. (1984). Pipeline and parallel-pipeline FFT processors for VLSI implementations. IEEE Transactions on Computers, C-33(5), 414\u2013426. \n                    https:\/\/doi.org\/10.1109\/TC.1984.1676458\n                    \n                  .","journal-title":"IEEE Transactions on Computers"},{"issue":"7","key":"1370_CR24","doi-asserted-by":"publisher","first-page":"585","DOI":"10.1109\/TCSII.2006.875306","volume":"53","author":"L Yang","year":"2006","unstructured":"Yang, L., Zhang, K., Liu, H., Huang, J., Huang, S. (2006). An efficient locally pipelined FFT processor. IEEE Transactions on Circuits and Systems II, 53(7), 585\u2013589. \n                    https:\/\/doi.org\/10.1109\/TCSII.2006.875306\n                    \n                  .","journal-title":"IEEE Transactions on Circuits and Systems II"},{"key":"1370_CR25","doi-asserted-by":"publisher","unstructured":"Zhong, G., Zheng, H., Jin, Z., Chen, D. (2011). Pang, Z.: 1024-point pipeline FFT processor with pointer FIFOs based on FPGA. In Proceedings of the IEEE\/IFIP international VLSI system-on-chip conference. \n                    https:\/\/doi.org\/10.1109\/VLSISOC.2011.6081654\n                    \n                   (pp. 122\u2013125).","DOI":"10.1109\/VLSISOC.2011.6081654"},{"key":"1370_CR26","doi-asserted-by":"publisher","first-page":"1","DOI":"10.1155\/2009\/219140","volume":"2009","author":"B Zhou","year":"2009","unstructured":"Zhou, B., Peng, Y., Hwang, D. (2009). Pipeline FFT architectures optimized for FPGAs. International Journal of Reconfigurable Computing, 2009, 1\u20139. \n                    https:\/\/doi.org\/10.1155\/2009\/219140\n                    \n                  .","journal-title":"International Journal of Reconfigurable Computing"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-018-1370-y\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1370-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1370-y.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,4,30]],"date-time":"2019-04-30T20:05:38Z","timestamp":1556654738000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-018-1370-y"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,5,1]]},"references-count":26,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2018,11]]}},"alternative-id":["1370"],"URL":"https:\/\/doi.org\/10.1007\/s11265-018-1370-y","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,5,1]]},"assertion":[{"value":"8 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 March 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"18 April 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"1 May 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}