{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,7,5]],"date-time":"2025-07-05T04:13:15Z","timestamp":1751688795464,"version":"3.41.0"},"reference-count":20,"publisher":"Springer Science and Business Media LLC","issue":"7","license":[{"start":{"date-parts":[[2018,5,31]],"date-time":"2018-05-31T00:00:00Z","timestamp":1527724800000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2019,7]]},"DOI":"10.1007\/s11265-018-1382-7","type":"journal-article","created":{"date-parts":[[2018,5,31]],"date-time":"2018-05-31T05:12:20Z","timestamp":1527743540000},"page":"745-757","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":9,"title":["Heterogeneous Computing Utilizing FPGAs"],"prefix":"10.1007","volume":"91","author":[{"given":"Marc","family":"Reichenbach","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Philipp","family":"Holzinger","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3114-8716","authenticated-orcid":false,"given":"Konrad","family":"H\u00e4ublein","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Tobias","family":"Lieske","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Paul","family":"Blinzer","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"297","published-online":{"date-parts":[[2018,5,31]]},"reference":[{"issue":"4","key":"1382_CR1","doi-asserted-by":"publisher","first-page":"34","DOI":"10.1145\/2927964.2927971","volume":"43","author":"D la Chevallerie de","year":"2016","unstructured":"de la Chevallerie, D., Korinth, J., Koch, A. (2016). Fflink: A Lightweight High-Performance Open-Source PCI Express Gen3 Interface for Reconfigurable Accelerators. SIGARCH Computer Architecture News, 43(4), 34\u201339.","journal-title":"SIGARCH Computer Architecture News"},{"key":"1382_CR2","doi-asserted-by":"crossref","unstructured":"Georgakoudis, G., Gillan, C., Hassan, A., Minhas, U.I., Spence, I.T.A., Tzenakis, G., Vandierendonck, H., Woods, R.F., Nikolopoulos, D.S., Shyamsundar, M., Barber, P., Russell, M., Bilas, A., Kaloutsakis, S., Giefers, H., Staar, P.W.J., Bekas, C., Horlock, N., Faloon, R., Pattison, C. (2016). Nanostreams Codesigned microservers for edge analytics in real time. SAMOS, pp. 180\u2013187.","DOI":"10.1109\/SAMOS.2016.7818346"},{"key":"1382_CR3","doi-asserted-by":"crossref","unstructured":"Glossner, J., Blinzer, P., Takala, J. (2015). HSA-Enabled DSPs and accelerators. In IEEE Global Conference on Signal and Information Processing (GlobalSIP) (pp. 1407\u20131411).","DOI":"10.1109\/GlobalSIP.2015.7418430"},{"key":"1382_CR4","doi-asserted-by":"crossref","unstructured":"Guidi, G., Reggiani, E., Tucci, L.D., Durelli, G., Blott, M., Santambrogio, M. (2016). On How to Improve FPGA-Based Systems Design Productivity via SDAccel. In 2016 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW) (pp. 247\u2013252).","DOI":"10.1109\/IPDPSW.2016.171"},{"key":"1382_CR5","volume-title":"Computer architecture fifth edition: a quantitative approach","author":"JL Hennessy","year":"2011","unstructured":"Hennessy, J.L., & Patterson, D.A. (2011). Computer architecture fifth edition: a quantitative approach, 5th ed. San Francisco: Morgan Kaufmann Publishers Inc.","edition":"5th ed"},{"key":"1382_CR6","unstructured":"HSA Foundation. (2016). HSA Foundation Specification Version 1.1."},{"key":"1382_CR7","unstructured":"HSA Foundation. (2016). HSA Platform System Architecture Specification 1.1."},{"key":"1382_CR8","unstructured":"HSA Foundation. (2016). HSA Programmer Reference Manual Specification 1.1."},{"key":"1382_CR9","unstructured":"HSA Foundation. (2016). HSA Runtime Specification 1.1.1."},{"key":"1382_CR10","unstructured":"Jaaskelainen, P., de La Lama, C.S., Huerta, P., Takala, J.H. (2010). OpenCL-based Design Methodology for Application-Specific Processors. In International Conference on Embedded Computer Systems (pp. 223\u2013230): IEEE."},{"key":"1382_CR11","doi-asserted-by":"crossref","unstructured":"Janik, I., Tang, Q., Khalid, M. (2015). An overview of Altera SDK for openCL A user perspective. In 2015 IEEE 28th Canadian Conference on Electrical and Computer Engineering (CCECE) (pp. 559\u2013564).","DOI":"10.1109\/CCECE.2015.7129336"},{"key":"1382_CR12","unstructured":"Heinrich, J. (1994). MIPS R4000 Microprocessor User\u2019s Manual."},{"issue":"4","key":"1382_CR13","doi-asserted-by":"publisher","first-page":"10","DOI":"10.1109\/MM.2017.3211105","volume":"37","author":"NS Kim","year":"2017","unstructured":"Kim, N.S., Chen, D., Xiong, J., Wen-mei, W.H. (2017). Heterogeneous computing meets Near-Memory acceleration and High-Level synthesis in the Post-Moore era. IEEE Micro, 37(4), 10\u201318.","journal-title":"IEEE Micro"},{"key":"1382_CR14","doi-asserted-by":"crossref","unstructured":"Mukherjee, S., Sun, Y., Blinzer, P., Ziabari, A.K., Kaeli, D. (2016). A comprehensive performance analysis of HSA and openCL 2.0. In IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) (pp. 183\u2013193).","DOI":"10.1109\/ISPASS.2016.7482093"},{"key":"1382_CR15","unstructured":"Radeon Technologies Group. (2017). Radeon\u2019s next-generation Vega architecture. Tech. rep., Advanced Micro Devices (AMD)."},{"key":"1382_CR16","doi-asserted-by":"crossref","unstructured":"Schmidt, M., Reichenbach, M., Fey, D. (2012). A Generic VHDL Template for 2D Stencil Code Applications on FPGAs. In 15th International Symposium on Object\/Component\/Service-Oriented Real-Time Distributed Computing Workshops (pp. 180\u2013187).","DOI":"10.1109\/ISORCW.2012.39"},{"key":"1382_CR17","unstructured":"Segal, O., Nasiri, N., Margala, M., Vanderbauwhede, W. (2014). High level programming of FPGAs for HPC and data centric applications. In 2014 IEEE High Performance Extreme Computing Conference (HPEC) (pp. 1\u20133): IEEE."},{"key":"1382_CR18","doi-asserted-by":"crossref","unstructured":"Severance, A., & Lemieux, G.G.F. Embedded Supercomputing in FPGAs with the VectorBlox MXP Matrix Processor. CODES+ISSS \u201913, IEEE Press, pp. 6:1\u20136:10.","DOI":"10.1109\/CODES-ISSS.2013.6658993"},{"key":"1382_CR19","unstructured":"Su, L.T. (2013). Architecting the future through heterogeneous computing. In IEEE International Solid-State Circuits Conference Digest of Technical Papers (pp. 8\u201311)."},{"key":"1382_CR20","doi-asserted-by":"crossref","unstructured":"Wu, Q., Ha, Y., Kumar, A., Luo, S., Li, A., Mohamed, S. A heterogeneous platform with GPU and FPGA for power efficient high performance computing. In 2014 14th International Symposium on Integrated Circuits (ISIC) (2014) (pp. 220\u2013223): IEEE.","DOI":"10.1109\/ISICIR.2014.7029447"}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1382-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-018-1382-7\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1382-7.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,4]],"date-time":"2025-07-04T22:09:02Z","timestamp":1751666942000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-018-1382-7"}},"subtitle":["A New and Flexible Approach Integrating Dedicated Hardware Accelerators into Common Computing Platforms"],"short-title":[],"issued":{"date-parts":[[2018,5,31]]},"references-count":20,"journal-issue":{"issue":"7","published-print":{"date-parts":[[2019,7]]}},"alternative-id":["1382"],"URL":"https:\/\/doi.org\/10.1007\/s11265-018-1382-7","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"type":"print","value":"1939-8018"},{"type":"electronic","value":"1939-8115"}],"subject":[],"published":{"date-parts":[[2018,5,31]]},"assertion":[{"value":"15 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"21 March 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"15 May 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"31 May 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}