{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,14]],"date-time":"2026-03-14T19:01:28Z","timestamp":1773514888070,"version":"3.50.1"},"reference-count":17,"publisher":"Springer Science and Business Media LLC","issue":"11","license":[{"start":{"date-parts":[[2018,6,12]],"date-time":"2018-06-12T00:00:00Z","timestamp":1528761600000},"content-version":"tdm","delay-in-days":0,"URL":"http:\/\/www.springer.com\/tdm"}],"content-domain":{"domain":["link.springer.com"],"crossmark-restriction":false},"short-container-title":["J Sign Process Syst"],"published-print":{"date-parts":[[2018,11]]},"DOI":"10.1007\/s11265-018-1387-2","type":"journal-article","created":{"date-parts":[[2018,6,12]],"date-time":"2018-06-12T06:29:28Z","timestamp":1528784968000},"page":"1593-1607","update-policy":"https:\/\/doi.org\/10.1007\/springer_crossmark_policy","source":"Crossref","is-referenced-by-count":6,"title":["Parallel Memory Accessing for FFT Architectures"],"prefix":"10.1007","volume":"90","author":[{"given":"V.","family":"Kitsakis","sequence":"first","affiliation":[]},{"given":"K.","family":"Nakos","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9265-3599","authenticated-orcid":false,"given":"D.","family":"Reisis","sequence":"additional","affiliation":[]},{"given":"N.","family":"Vlassopoulos","sequence":"additional","affiliation":[]}],"member":"297","published-online":{"date-parts":[[2018,6,12]]},"reference":[{"issue":"3","key":"1387_CR1","doi-asserted-by":"publisher","first-page":"213","DOI":"10.1109\/TC.1980.1675553","volume":"C-29","author":"DS Parker","year":"1980","unstructured":"Parker, D.S. (1980). Notes on Shuffle\/Exchange-Type Switching Networks. IEEE Transactions on Computers, C-29(3), 213\u2013222.","journal-title":"IEEE Transactions on Computers"},{"key":"1387_CR2","doi-asserted-by":"publisher","first-page":"414","DOI":"10.1109\/TC.1984.1676458","volume":"C-33","author":"EH Wold","year":"1984","unstructured":"Wold, E.H., & Despain, A.M. (1984). Pipeline and Parallel FFT Processors for VLSI Implementations. IEEE Transactions on Computers, C-33, 414\u2013426.","journal-title":"IEEE Transactions on Computers"},{"issue":"5","key":"1387_CR3","doi-asserted-by":"publisher","first-page":"312","DOI":"10.1109\/82.142032","volume":"39","author":"LG Johnson","year":"1992","unstructured":"Johnson, L.G. (1992). Conflict Free Memory Addressing for Dedicated FFT Hardware. IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing, 39(5), 312\u2013316.","journal-title":"IEEE Transactions on Circuits and Systems - II: Analog and Digital Signal Processing"},{"issue":"3","key":"1387_CR4","doi-asserted-by":"publisher","first-page":"907","DOI":"10.1109\/78.747802","volume":"47","author":"Y Ma","year":"1999","unstructured":"Ma, Y. (1999). An effective memory addressing scheme for FFT processors. IEEE Transactions on Signal Processing, 47(3), 907\u2013911.","journal-title":"IEEE Transactions on Signal Processing"},{"issue":"11","key":"1387_CR5","doi-asserted-by":"publisher","first-page":"1149","DOI":"10.1109\/TCSII.2008.2004540","volume":"55","author":"X Xiao","year":"2008","unstructured":"Xiao, X., Oruklu, E., Saniie, J. (2008). An efficient FFT engine with reduced addressing logic. IEEE Transactions on Circuits and Systems II: Express Briefs, 55(11), 1149\u20131153.","journal-title":"IEEE Transactions on Circuits and Systems II: Express Briefs"},{"key":"1387_CR6","doi-asserted-by":"crossref","unstructured":"Takala, J.H., J\u00e4rvinen, T.S., Sorokin, H.T. (2003). Conflict-Free Parallel Memory Access Scheme for FFT Processors. In The Proceedings of the Intelligent Symposium on Circuits and Systems, ISCAS, (Vol. 4 pp. 524\u2013527).","DOI":"10.1109\/ISCAS.2003.1205957"},{"issue":"11","key":"1387_CR7","doi-asserted-by":"publisher","first-page":"3438","DOI":"10.1109\/TCSI.2008.924889","volume":"55","author":"D Reisis","year":"2008","unstructured":"Reisis, D., & Vlassopoulos, N. (2008). Conflict free parallel memory accessing techniques for FFT architectures. IEEE Transactions on Circuits and Systems I, 55(11), 3438\u20133447.","journal-title":"IEEE Transactions on Circuits and Systems I"},{"key":"1387_CR8","doi-asserted-by":"crossref","unstructured":"Nakos, K., Reisis, D., Vlassopoulos, N. (2008). Addressing technique for parallel memory accessing in Radix-2 FFT processors. In The Proceedings of the IEEE ICECS (pp. 52\u201356).","DOI":"10.1109\/ICECS.2008.4674789"},{"key":"1387_CR9","doi-asserted-by":"publisher","first-page":"474","DOI":"10.1145\/321526.321536","volume":"16","author":"M Pease","year":"1969","unstructured":"Pease, M. (1969). Organization of large scale Fourier transforms. Journal of the ACM, 16, 474\u2013482.","journal-title":"Journal of the ACM"},{"key":"1387_CR10","doi-asserted-by":"publisher","first-page":"577","DOI":"10.1109\/TASSP.1976.1162854","volume":"ASSP-24","author":"D Cohen","year":"1976","unstructured":"Cohen, D. (1976). Simplified control of FFT hardware. IEEE Transactions on Acoustics, Speech, and Signal Processing, ASSP-24, 577\u2013579.","journal-title":"IEEE Transactions on Acoustics, Speech, and Signal Processing"},{"issue":"2","key":"1387_CR11","doi-asserted-by":"publisher","first-page":"10","DOI":"10.1145\/1502793.1502799","volume":"56","author":"M P\u00fcschel","year":"2009","unstructured":"P\u00fcschel, M., Milder, P.A., Coe, J.C. (2009). Permuting streaming data using RAMs. Journal of the ACM, 56(2), 10.","journal-title":"Journal of the ACM"},{"key":"1387_CR12","first-page":"10","volume":"60","author":"M Ayinala","year":"2013","unstructured":"Ayinala, M., Lao, Y., Parhi, K.K. (2013). An in-place FFT architecture for real-valued signals. IEEE Transactions on Circuits and Systems\u2014II: Express Briefs, 60, 10.","journal-title":"IEEE Transactions on Circuits and Systems\u2014II: Express Briefs"},{"issue":"5","key":"1387_CR13","doi-asserted-by":"publisher","first-page":"911","DOI":"10.1109\/TCSI.2005.846667","volume":"52","author":"BG Jo","year":"2005","unstructured":"Jo, B.G., & Sunwoo, M.H. (2005). New continuous-flow mixed-radix (CFMR) FFT processor using novel in-place strategy. Transactions on Circuits and Systems I, 52(5), 911\u2013919.","journal-title":"Transactions on Circuits and Systems I"},{"key":"1387_CR14","doi-asserted-by":"crossref","unstructured":"Jacobson, A.T., Truong, D.N., Baas, D.M. (2009). The design of a reconfigurable continuous-flow mixed-radix FFT processor. In ISCAS 2009 IEEE International Symposium on Circuits and Systems.","DOI":"10.1109\/ISCAS.2009.5117960"},{"key":"1387_CR15","unstructured":"Rabaey, J.M., Chandrakasan, A., Nikolic, B. (2003). Digital Integrated Circuits, Pearson. ISBN-13 978-0130909961."},{"key":"1387_CR16","unstructured":"Franchetti, F., & Puschel, M. (2011). Fast Fourier Transform Encyclopedia of Parallel Computing. ISBN 978-0-387-09765-7."},{"key":"1387_CR17","unstructured":"DFT\/FFT IP Core Generator, \n                    http:\/\/www.spiral.net\/hardware\/dftgen.html\n                    \n                  ."}],"container-title":["Journal of Signal Processing Systems"],"original-title":[],"language":"en","link":[{"URL":"http:\/\/link.springer.com\/article\/10.1007\/s11265-018-1387-2\/fulltext.html","content-type":"text\/html","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1387-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"text-mining"},{"URL":"http:\/\/link.springer.com\/content\/pdf\/10.1007\/s11265-018-1387-2.pdf","content-type":"application\/pdf","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2019,6,11]],"date-time":"2019-06-11T19:21:55Z","timestamp":1560280915000},"score":1,"resource":{"primary":{"URL":"http:\/\/link.springer.com\/10.1007\/s11265-018-1387-2"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,6,12]]},"references-count":17,"journal-issue":{"issue":"11","published-print":{"date-parts":[[2018,11]]}},"alternative-id":["1387"],"URL":"https:\/\/doi.org\/10.1007\/s11265-018-1387-2","relation":{},"ISSN":["1939-8018","1939-8115"],"issn-type":[{"value":"1939-8018","type":"print"},{"value":"1939-8115","type":"electronic"}],"subject":[],"published":{"date-parts":[[2018,6,12]]},"assertion":[{"value":"1 December 2017","order":1,"name":"received","label":"Received","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"8 March 2018","order":2,"name":"revised","label":"Revised","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"30 May 2018","order":3,"name":"accepted","label":"Accepted","group":{"name":"ArticleHistory","label":"Article History"}},{"value":"12 June 2018","order":4,"name":"first_online","label":"First Online","group":{"name":"ArticleHistory","label":"Article History"}}]}}